ARM64: meson: Sync DT and Bindings with Linux 4.16
Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.16.0. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
Tom Rini
parent
f0f3762cb7
commit
7d750c3520
@ -211,32 +211,39 @@
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#size-cells = <2>;
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ranges;
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cbus: cbus@c1100000 {
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cbus: bus@c1100000 {
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compatible = "simple-bus";
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reg = <0x0 0xc1100000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
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gpio_intc: interrupt-controller@9880 {
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compatible = "amlogic,meson-gpio-intc";
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reg = <0x0 0x9880 0x0 0x10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
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status = "disabled";
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};
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reset: reset-controller@4404 {
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compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
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reg = <0x0 0x04404 0x0 0x20>;
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reg = <0x0 0x04404 0x0 0x9c>;
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#reset-cells = <1>;
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};
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uart_A: serial@84c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x84c0 0x0 0x14>;
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compatible = "amlogic,meson-gx-uart";
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reg = <0x0 0x84c0 0x0 0x18>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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uart_B: serial@84dc {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x84dc 0x0 0x14>;
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compatible = "amlogic,meson-gx-uart";
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reg = <0x0 0x84dc 0x0 0x18>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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@ -279,10 +286,9 @@
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};
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uart_C: serial@8700 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x8700 0x0 0x14>;
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compatible = "amlogic,meson-gx-uart";
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reg = <0x0 0x8700 0x0 0x18>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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@ -360,33 +366,53 @@
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};
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};
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aobus: aobus@c8100000 {
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aobus: bus@c8100000 {
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compatible = "simple-bus";
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reg = <0x0 0xc8100000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
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clkc_AO: clock-controller@040 {
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compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
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reg = <0x0 0x00040 0x0 0x4>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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sysctrl_AO: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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reg = <0x0 0x0 0x0 0x100>;
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pwrc_vpu: power-controller-vpu {
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compatible = "amlogic,meson-gx-pwrc-vpu";
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#power-domain-cells = <0>;
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amlogic,hhi-sysctrl = <&sysctrl>;
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};
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-gx-aoclkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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cec_AO: cec@100 {
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compatible = "amlogic,meson-gx-ao-cec";
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reg = <0x0 0x00100 0x0 0x14>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
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};
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sec_AO: ao-secure@140 {
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compatible = "amlogic,meson-gx-ao-secure", "syscon";
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reg = <0x0 0x140 0x0 0x140>;
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amlogic,has-chip-id;
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};
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uart_AO: serial@4c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x004c0 0x0 0x14>;
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x004c0 0x0 0x18>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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uart_AO_B: serial@4e0 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x004e0 0x0 0x14>;
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x004e0 0x0 0x18>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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@ -427,19 +453,24 @@
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};
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};
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hiubus: hiubus@c883c000 {
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hiubus: bus@c883c000 {
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compatible = "simple-bus";
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reg = <0x0 0xc883c000 0x0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
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sysctrl: system-controller@0 {
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compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
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reg = <0 0 0 0x400>;
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};
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mailbox: mailbox@404 {
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compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
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reg = <0 0x404 0 0x4c>;
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interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
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<0 209 IRQ_TYPE_EDGE_RISING>,
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<0 210 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
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#mbox-cells = <1>;
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};
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};
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@ -448,7 +479,7 @@
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compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
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reg = <0x0 0xc9410000 0x0 0x10000
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0x0 0xc8834540 0x0 0x4>;
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interrupts = <0 8 1>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "macirq";
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status = "disabled";
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};
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@ -50,7 +50,7 @@
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/ {
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compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
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model = "Hardkernel ODROID-C2";
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aliases {
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serial0 = &uart_AO;
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};
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@ -135,6 +135,24 @@
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_tmds_out>;
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};
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};
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};
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};
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&cec_AO {
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status = "okay";
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pinctrl-0 = <&ao_cec_pins>;
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pinctrl-names = "default";
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hdmi-phandle = <&hdmi_tx>;
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};
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ðmac {
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@ -156,7 +174,11 @@
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#size-cells = <0>;
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eth_phy0: ethernet-phy@0 {
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/* Realtek RTL8211F (0x001cc916) */
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reg = <0>;
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interrupt-parent = <&gpio_intc>;
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/* MAC_INTR on GPIOZ_15 */
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interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
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eee-broken-1000t;
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};
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};
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@ -177,6 +199,18 @@
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};
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};
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&hdmi_tx {
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status = "okay";
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pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
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pinctrl-names = "default";
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};
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&hdmi_tx_tmds_port {
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hdmi_tx_tmds_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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&i2c_A {
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status = "okay";
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pinctrl-0 = <&i2c_a_pins>;
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@ -194,7 +228,9 @@
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"USB HUB nRESET", "USB OTG Power En",
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"J7 Header Pin2", "IR In", "J7 Header Pin4",
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"J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
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"HDMI CEC", "SYS LED";
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"HDMI CEC", "SYS LED",
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/* GPIO_TEST_N */
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"";
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};
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&pinctrl_periphs {
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@ -233,11 +269,9 @@
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"J2 Header Pin12", "J2 Header Pin13",
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"J2 Header Pin8", "J2 Header Pin10",
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"", "", "", "", "",
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"J2 Header Pin11", "", "J2 Header Pin7",
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"J2 Header Pin11", "", "J2 Header Pin7", "",
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/* Bank GPIOCLK */
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"", "", "", "",
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/* GPIO_TEST_N */
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"";
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"", "", "", "";
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};
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&saradc {
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@ -253,7 +287,8 @@
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&sd_emmc_b {
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status = "okay";
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pinctrl-0 = <&sdcard_pins>;
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pinctrl-names = "default";
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pinctrl-1 = <&sdcard_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <4>;
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cap-sd-highspeed;
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@ -270,11 +305,11 @@
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <8>;
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cap-sd-highspeed;
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max-frequency = <200000000>;
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non-removable;
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disable-wp;
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@ -300,6 +335,7 @@
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&usb1_phy {
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status = "okay";
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phy-supply = <&usb_otg_pwr>;
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};
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&usb0 {
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@ -307,6 +307,15 @@
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};
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};
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&cec_AO {
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clocks = <&clkc_AO CLKID_AO_CEC_32K>;
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clock-names = "core";
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};
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&clkc_AO {
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compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
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};
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ðmac {
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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@ -314,6 +323,12 @@
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clock-names = "stmmaceth", "clkin0", "clkin1";
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};
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&gpio_intc {
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compatible = "amlogic,meson-gpio-intc",
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"amlogic,meson-gxbb-gpio-intc";
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status = "okay";
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};
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&hdmi_tx {
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compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
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resets = <&reset RESET_HDMITX_CAPB3>,
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@ -370,19 +385,36 @@
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_periphs 0 14 120>;
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gpio-ranges = <&pinctrl_periphs 0 0 119>;
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};
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emmc_pins: emmc {
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mux {
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groups = "emmc_nand_d07",
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"emmc_cmd",
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"emmc_clk",
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"emmc_ds";
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"emmc_clk";
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function = "emmc";
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};
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};
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emmc_ds_pins: emmc-ds {
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mux {
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groups = "emmc_ds";
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function = "emmc";
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};
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};
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emmc_clk_gate_pins: emmc_clk_gate {
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mux {
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groups = "BOOT_8";
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function = "gpio_periphs";
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};
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cfg-pull-down {
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pins = "BOOT_8";
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bias-pull-down;
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};
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};
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nor_pins: nor {
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mux {
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groups = "nor_d",
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@ -421,6 +453,17 @@
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};
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};
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sdcard_clk_gate_pins: sdcard_clk_gate {
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mux {
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groups = "CARD_2";
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function = "gpio_periphs";
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};
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cfg-pull-down {
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pins = "CARD_2";
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bias-pull-down;
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};
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};
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sdio_pins: sdio {
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mux {
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groups = "sdio_d0",
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@ -433,6 +476,17 @@
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};
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};
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sdio_clk_gate_pins: sdio_clk_gate {
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mux {
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groups = "GPIOX_4";
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function = "gpio_periphs";
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};
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cfg-pull-down {
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pins = "GPIOX_4";
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bias-pull-down;
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};
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};
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sdio_irq_pins: sdio_irq {
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mux {
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groups = "sdio_irq";
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@ -640,33 +694,74 @@
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};
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};
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&pwrc_vpu {
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resets = <&reset RESET_VIU>,
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<&reset RESET_VENC>,
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<&reset RESET_VCBUS>,
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<&reset RESET_BT656>,
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<&reset RESET_DVIN_RESET>,
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<&reset RESET_RDMA>,
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<&reset RESET_VENCI>,
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<&reset RESET_VENCP>,
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<&reset RESET_VDAC>,
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<&reset RESET_VDI6>,
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<&reset RESET_VENCL>,
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<&reset RESET_VID_LOCK>;
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clocks = <&clkc CLKID_VPU>,
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<&clkc CLKID_VAPB>;
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clock-names = "vpu", "vapb";
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/*
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* VPU clocking is provided by two identical clock paths
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* VPU_0 and VPU_1 muxed to a single clock by a glitch
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* free mux to safely change frequency while running.
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* Same for VAPB but with a final gate after the glitch free mux.
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*/
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assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_VPU>, /* Glitch free mux */
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<&clkc CLKID_VAPB_0_SEL>,
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<&clkc CLKID_VAPB_0>,
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<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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<0>, /* Do Nothing */
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_FCLK_DIV4>,
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<0>, /* Do Nothing */
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<&clkc CLKID_VAPB_0>;
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assigned-clock-rates = <0>, /* Do Nothing */
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<666666666>,
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<0>, /* Do Nothing */
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<0>, /* Do Nothing */
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<250000000>,
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<0>; /* Do Nothing */
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};
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&saradc {
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compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
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clocks = <&xtal>,
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<&clkc CLKID_SAR_ADC>,
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<&clkc CLKID_SANA>,
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<&clkc CLKID_SAR_ADC_CLK>,
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<&clkc CLKID_SAR_ADC_SEL>;
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clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
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clock-names = "clkin", "core", "adc_clk", "adc_sel";
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};
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&sd_emmc_a {
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clocks = <&clkc CLKID_SD_EMMC_A>,
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<&xtal>,
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<&clkc CLKID_SD_EMMC_A_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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};
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&sd_emmc_b {
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clocks = <&clkc CLKID_SD_EMMC_B>,
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<&xtal>,
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<&clkc CLKID_SD_EMMC_B_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
};
|
||||
|
||||
&sd_emmc_c {
|
||||
clocks = <&clkc CLKID_SD_EMMC_C>,
|
||||
<&xtal>,
|
||||
<&clkc CLKID_SD_EMMC_C_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
};
|
||||
@ -682,6 +777,32 @@
|
||||
clocks = <&clkc CLKID_SPI>;
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_AO_B {
|
||||
clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_B {
|
||||
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_C {
|
||||
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&vpu {
|
||||
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
|
||||
power-domains = <&pwrc_vpu>;
|
||||
};
|
||||
|
||||
@ -66,6 +66,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&ao_cec_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
|
||||
@ -104,6 +111,62 @@
|
||||
linux,rc-map-name = "rc-geekbox";
|
||||
};
|
||||
|
||||
&pinctrl_aobus {
|
||||
gpio-line-names = "UART TX",
|
||||
"UART RX",
|
||||
"Power Key In",
|
||||
"J9 Header Pin35",
|
||||
"J9 Header Pin16",
|
||||
"J9 Header Pin15",
|
||||
"J9 Header Pin33",
|
||||
"IR In",
|
||||
"HDMI CEC",
|
||||
"SYS LED",
|
||||
/* GPIO_TEST_N */
|
||||
"";
|
||||
};
|
||||
|
||||
&pinctrl_periphs {
|
||||
gpio-line-names = /* Bank GPIOZ */
|
||||
"", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "",
|
||||
"Power OFF",
|
||||
"VCCK Enable",
|
||||
/* Bank GPIOH */
|
||||
"HDMI HPD", "HDMI SDA", "HDMI SCL",
|
||||
"HDMI_5V_EN", "SPDIF",
|
||||
"J9 Header Pin37",
|
||||
"J9 Header Pin30",
|
||||
"J9 Header Pin29",
|
||||
"J9 Header Pin32",
|
||||
"J9 Header Pin31",
|
||||
/* Bank BOOT */
|
||||
"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
|
||||
"eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
|
||||
"eMMC Clk", "eMMC Reset", "eMMC CMD",
|
||||
"", "BOOT_MODE", "", "", "eMMC Data Strobe",
|
||||
/* Bank CARD */
|
||||
"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
|
||||
"SDCard D3", "SDCard D2", "SDCard Det",
|
||||
/* Bank GPIODV */
|
||||
"", "", "", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "", "", "",
|
||||
"I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
|
||||
"VCCK Regulator", "VDDEE Regulator",
|
||||
/* Bank GPIOX */
|
||||
"WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
|
||||
"WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
|
||||
"WIFI Power Enable", "WIFI WAKE HOST",
|
||||
"Bluetooth PCM DOUT", "Bluetooth PCM DIN",
|
||||
"Bluetooth PCM SYNC", "Bluetooth PCM CLK",
|
||||
"Bluetooth UART TX", "Bluetooth UART RX",
|
||||
"Bluetooth UART CTS", "Bluetooth UART RTS",
|
||||
"WIFI 32K", "Bluetooth Enable",
|
||||
"Bluetooth WAKE HOST",
|
||||
/* Bank GPIOCLK */
|
||||
"", "J9 Header Pin39";
|
||||
};
|
||||
|
||||
&pwm_AO_ab {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
|
||||
|
||||
@ -71,6 +71,18 @@
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
hdmi_5v: regulator-hdmi-5v {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "HDMI_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_3v3: regulator-vcc_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3";
|
||||
@ -90,6 +102,16 @@
|
||||
|
||||
states = <3300000 0>,
|
||||
<1800000 1>;
|
||||
|
||||
regulator-settling-time-up-us = <200>;
|
||||
regulator-settling-time-down-us = <50000>;
|
||||
};
|
||||
|
||||
vddio_ao18: regulator-vddio_ao18 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_AO18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
@ -100,6 +122,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&ao_cec_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cvbs_vdac_port {
|
||||
cvbs_vdac_out: endpoint {
|
||||
remote-endpoint = <&cvbs_connector_in>;
|
||||
@ -110,6 +139,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&internal_phy {
|
||||
pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
@ -128,14 +162,80 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_aobus {
|
||||
gpio-line-names = "UART TX",
|
||||
"UART RX",
|
||||
"Blue LED",
|
||||
"SDCard Voltage Switch",
|
||||
"7J1 Header Pin5",
|
||||
"7J1 Header Pin3",
|
||||
"7J1 Header Pin12",
|
||||
"IR In",
|
||||
"9J3 Switch HDMI CEC/7J1 Header Pin11",
|
||||
"7J1 Header Pin13",
|
||||
/* GPIO_TEST_N */
|
||||
"7J1 Header Pin15";
|
||||
};
|
||||
|
||||
&pinctrl_periphs {
|
||||
gpio-line-names = /* Bank GPIOZ */
|
||||
"", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "",
|
||||
"Eth Link LED", "Eth Activity LED",
|
||||
/* Bank GPIOH */
|
||||
"HDMI HPD", "HDMI SDA", "HDMI SCL",
|
||||
"HDMI_5V_EN", "9J1 Header Pin2",
|
||||
"Analog Audio Mute",
|
||||
"2J3 Header Pin6",
|
||||
"2J3 Header Pin5",
|
||||
"2J3 Header Pin4",
|
||||
"2J3 Header Pin3",
|
||||
/* Bank BOOT */
|
||||
"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
|
||||
"eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
|
||||
"eMMC Clk", "eMMC Reset", "eMMC CMD",
|
||||
"ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
|
||||
/* Bank CARD */
|
||||
"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
|
||||
"SDCard D3", "SDCard D2", "SDCard Det",
|
||||
/* Bank GPIODV */
|
||||
"", "", "", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "", "", "",
|
||||
"Green LED", "VCCK Enable",
|
||||
"7J1 Header Pin27", "7J1 Header Pin28",
|
||||
"VCCK Regulator", "VDDEE Regulator",
|
||||
/* Bank GPIOX */
|
||||
"7J1 Header Pin22", "7J1 Header Pin26",
|
||||
"7J1 Header Pin36", "7J1 Header Pin38",
|
||||
"7J1 Header Pin40", "7J1 Header Pin37",
|
||||
"7J1 Header Pin33", "7J1 Header Pin35",
|
||||
"7J1 Header Pin19", "7J1 Header Pin21",
|
||||
"7J1 Header Pin24", "7J1 Header Pin23",
|
||||
"7J1 Header Pin8", "7J1 Header Pin10",
|
||||
"7J1 Header Pin16", "7J1 Header Pin18",
|
||||
"7J1 Header Pin32", "7J1 Header Pin29",
|
||||
"7J1 Header Pin31",
|
||||
/* Bank GPIOCLK */
|
||||
"7J1 Header Pin7", "";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vddio_ao18>;
|
||||
};
|
||||
|
||||
/* SD card */
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcard_pins>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-1 = <&sdcard_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
max-frequency = <100000000>;
|
||||
disable-wp;
|
||||
|
||||
@ -149,11 +249,13 @@
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-3_3v;
|
||||
max-frequency = <50000000>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
||||
@ -71,6 +71,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&ao_cec_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cvbs_vdac_port {
|
||||
cvbs_vdac_out: endpoint {
|
||||
remote-endpoint = <&cvbs_connector_in>;
|
||||
|
||||
@ -27,6 +27,18 @@
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
hdmi_5v: regulator-hdmi-5v {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "HDMI_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_BOOT";
|
||||
@ -94,7 +106,8 @@
|
||||
&sd_emmc_a {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-1 = <&sdio_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -115,7 +128,8 @@
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcard_pins>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-1 = <&sdcard_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
@ -132,11 +146,11 @@
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
|
||||
@ -43,11 +43,20 @@
|
||||
|
||||
#include "meson-gx.dtsi"
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
#include <dt-bindings/clock/gxbb-aoclkc.h>
|
||||
#include <dt-bindings/gpio/meson-gxl-gpio.h>
|
||||
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,meson-gxl";
|
||||
|
||||
reserved-memory {
|
||||
/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
|
||||
secmon_reserved_alt: secmon@5000000 {
|
||||
reg = <0x0 0x05000000 0x0 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
@ -207,6 +216,21 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
clocks = <&clkc_AO CLKID_AO_CEC_32K>;
|
||||
clock-names = "core";
|
||||
};
|
||||
|
||||
&clkc_AO {
|
||||
compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
|
||||
};
|
||||
|
||||
&gpio_intc {
|
||||
compatible = "amlogic,meson-gpio-intc",
|
||||
"amlogic,meson-gxl-gpio-intc";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
|
||||
resets = <&reset RESET_HDMITX_CAPB3>,
|
||||
@ -258,19 +282,36 @@
|
||||
reg-names = "mux", "pull", "pull-enable", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_periphs 0 10 101>;
|
||||
gpio-ranges = <&pinctrl_periphs 0 0 100>;
|
||||
};
|
||||
|
||||
emmc_pins: emmc {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_cmd",
|
||||
"emmc_clk",
|
||||
"emmc_ds";
|
||||
"emmc_clk";
|
||||
function = "emmc";
|
||||
};
|
||||
};
|
||||
|
||||
emmc_ds_pins: emmc-ds {
|
||||
mux {
|
||||
groups = "emmc_ds";
|
||||
function = "emmc";
|
||||
};
|
||||
};
|
||||
|
||||
emmc_clk_gate_pins: emmc_clk_gate {
|
||||
mux {
|
||||
groups = "BOOT_8";
|
||||
function = "gpio_periphs";
|
||||
};
|
||||
cfg-pull-down {
|
||||
pins = "BOOT_8";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
nor_pins: nor {
|
||||
mux {
|
||||
groups = "nor_d",
|
||||
@ -309,6 +350,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
sdcard_clk_gate_pins: sdcard_clk_gate {
|
||||
mux {
|
||||
groups = "CARD_2";
|
||||
function = "gpio_periphs";
|
||||
};
|
||||
cfg-pull-down {
|
||||
pins = "CARD_2";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins: sdio {
|
||||
mux {
|
||||
groups = "sdio_d0",
|
||||
@ -321,6 +373,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
sdio_clk_gate_pins: sdio_clk_gate {
|
||||
mux {
|
||||
groups = "GPIOX_4";
|
||||
function = "gpio_periphs";
|
||||
};
|
||||
cfg-pull-down {
|
||||
pins = "GPIOX_4";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_irq_pins: sdio_irq {
|
||||
mux {
|
||||
groups = "sdio_irq";
|
||||
@ -568,6 +631,7 @@
|
||||
|
||||
internal_phy: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <8>;
|
||||
max-speed = <100>;
|
||||
};
|
||||
@ -581,33 +645,74 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pwrc_vpu {
|
||||
resets = <&reset RESET_VIU>,
|
||||
<&reset RESET_VENC>,
|
||||
<&reset RESET_VCBUS>,
|
||||
<&reset RESET_BT656>,
|
||||
<&reset RESET_DVIN_RESET>,
|
||||
<&reset RESET_RDMA>,
|
||||
<&reset RESET_VENCI>,
|
||||
<&reset RESET_VENCP>,
|
||||
<&reset RESET_VDAC>,
|
||||
<&reset RESET_VDI6>,
|
||||
<&reset RESET_VENCL>,
|
||||
<&reset RESET_VID_LOCK>;
|
||||
clocks = <&clkc CLKID_VPU>,
|
||||
<&clkc CLKID_VAPB>;
|
||||
clock-names = "vpu", "vapb";
|
||||
/*
|
||||
* VPU clocking is provided by two identical clock paths
|
||||
* VPU_0 and VPU_1 muxed to a single clock by a glitch
|
||||
* free mux to safely change frequency while running.
|
||||
* Same for VAPB but with a final gate after the glitch free mux.
|
||||
*/
|
||||
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
|
||||
<&clkc CLKID_VPU_0>,
|
||||
<&clkc CLKID_VPU>, /* Glitch free mux */
|
||||
<&clkc CLKID_VAPB_0_SEL>,
|
||||
<&clkc CLKID_VAPB_0>,
|
||||
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
|
||||
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_VPU_0>,
|
||||
<&clkc CLKID_FCLK_DIV4>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_VAPB_0>;
|
||||
assigned-clock-rates = <0>, /* Do Nothing */
|
||||
<666666666>,
|
||||
<0>, /* Do Nothing */
|
||||
<0>, /* Do Nothing */
|
||||
<250000000>,
|
||||
<0>; /* Do Nothing */
|
||||
};
|
||||
|
||||
&saradc {
|
||||
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
|
||||
clocks = <&xtal>,
|
||||
<&clkc CLKID_SAR_ADC>,
|
||||
<&clkc CLKID_SANA>,
|
||||
<&clkc CLKID_SAR_ADC_CLK>,
|
||||
<&clkc CLKID_SAR_ADC_SEL>;
|
||||
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
|
||||
clock-names = "clkin", "core", "adc_clk", "adc_sel";
|
||||
};
|
||||
|
||||
&sd_emmc_a {
|
||||
clocks = <&clkc CLKID_SD_EMMC_A>,
|
||||
<&xtal>,
|
||||
<&clkc CLKID_SD_EMMC_A_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
};
|
||||
|
||||
&sd_emmc_b {
|
||||
clocks = <&clkc CLKID_SD_EMMC_B>,
|
||||
<&xtal>,
|
||||
<&clkc CLKID_SD_EMMC_B_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
};
|
||||
|
||||
&sd_emmc_c {
|
||||
clocks = <&clkc CLKID_SD_EMMC_C>,
|
||||
<&xtal>,
|
||||
<&clkc CLKID_SD_EMMC_C_CLK0>,
|
||||
<&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
};
|
||||
@ -623,6 +728,32 @@
|
||||
clocks = <&clkc CLKID_SPI>;
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_AO_B {
|
||||
clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_B {
|
||||
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&uart_C {
|
||||
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
};
|
||||
|
||||
&vpu {
|
||||
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
|
||||
power-domains = <&pwrc_vpu>;
|
||||
};
|
||||
|
||||
@ -62,5 +62,6 @@
|
||||
#define CLKID_AO_UART1 3
|
||||
#define CLKID_AO_UART2 4
|
||||
#define CLKID_AO_IR_BLASTER 5
|
||||
#define CLKID_AO_CEC_32K 6
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* GXBB clock tree IDs
|
||||
*/
|
||||
@ -5,37 +6,96 @@
|
||||
#ifndef __GXBB_CLKC_H
|
||||
#define __GXBB_CLKC_H
|
||||
|
||||
#define CLKID_SYS_PLL 0
|
||||
#define CLKID_HDMI_PLL 2
|
||||
#define CLKID_FIXED_PLL 3
|
||||
#define CLKID_FCLK_DIV2 4
|
||||
#define CLKID_FCLK_DIV3 5
|
||||
#define CLKID_FCLK_DIV4 6
|
||||
#define CLKID_FCLK_DIV5 7
|
||||
#define CLKID_FCLK_DIV7 8
|
||||
#define CLKID_GP0_PLL 9
|
||||
#define CLKID_CLK81 12
|
||||
#define CLKID_MPLL0 13
|
||||
#define CLKID_MPLL1 14
|
||||
#define CLKID_MPLL2 15
|
||||
#define CLKID_DDR 16
|
||||
#define CLKID_DOS 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_SAR_ADC 23
|
||||
#define CLKID_SMART_CARD 24
|
||||
#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SDHC 27
|
||||
#define CLKID_STREAM 28
|
||||
#define CLKID_ASYNC_FIFO 29
|
||||
#define CLKID_SDIO 30
|
||||
#define CLKID_ABUF 31
|
||||
#define CLKID_HIU_IFACE 32
|
||||
#define CLKID_ASSIST_MISC 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_I2S_SPDIF 35
|
||||
#define CLKID_DEMUX 37
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
#define CLKID_I2S_OUT 40
|
||||
#define CLKID_AMCLK 41
|
||||
#define CLKID_AIFIFO2 42
|
||||
#define CLKID_MIXER 43
|
||||
#define CLKID_MIXER_IFACE 44
|
||||
#define CLKID_ADC 45
|
||||
#define CLKID_BLKMV 46
|
||||
#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_G2D 49
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_RESET 52
|
||||
#define CLKID_NAND 53
|
||||
#define CLKID_DOS_PARSER 54
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_VDIN1 56
|
||||
#define CLKID_AHB_ARB0 57
|
||||
#define CLKID_EFUSE 58
|
||||
#define CLKID_BOOT_ROM 59
|
||||
#define CLKID_AHB_DATA_BUS 60
|
||||
#define CLKID_AHB_CTRL_BUS 61
|
||||
#define CLKID_HDMI_INTR_SYNC 62
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
#define CLKID_CLK81_A53 72
|
||||
#define CLKID_VCLK2_VENCI0 73
|
||||
#define CLKID_VCLK2_VENCI1 74
|
||||
#define CLKID_VCLK2_VENCP0 75
|
||||
#define CLKID_VCLK2_VENCP1 76
|
||||
#define CLKID_GCLK_VENCI_INT0 77
|
||||
#define CLKID_GCLK_VENCI_INT 78
|
||||
#define CLKID_DAC_CLK 79
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
#define CLKID_IEC958_GATE 81
|
||||
#define CLKID_ENC480P 82
|
||||
#define CLKID_RNG1 83
|
||||
#define CLKID_GCLK_VENCI_INT1 84
|
||||
#define CLKID_VCLK2_VENCLMCC 85
|
||||
#define CLKID_VCLK2_VENCL 86
|
||||
#define CLKID_VCLK_OTHER 87
|
||||
#define CLKID_EDP 88
|
||||
#define CLKID_AO_MEDIA_CPU 89
|
||||
#define CLKID_AO_AHB_SRAM 90
|
||||
#define CLKID_AO_AHB_BUS 91
|
||||
#define CLKID_AO_IFACE 92
|
||||
#define CLKID_AO_I2C 93
|
||||
#define CLKID_SD_EMMC_A 94
|
||||
#define CLKID_SD_EMMC_B 95
|
||||
@ -50,5 +110,20 @@
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
#define CLKID_CTS_I958 113
|
||||
#define CLKID_32K_CLK 114
|
||||
#define CLKID_SD_EMMC_A_CLK0 119
|
||||
#define CLKID_SD_EMMC_B_CLK0 122
|
||||
#define CLKID_SD_EMMC_C_CLK0 125
|
||||
#define CLKID_VPU_0_SEL 126
|
||||
#define CLKID_VPU_0 128
|
||||
#define CLKID_VPU_1_SEL 129
|
||||
#define CLKID_VPU_1 131
|
||||
#define CLKID_VPU 132
|
||||
#define CLKID_VAPB_0_SEL 133
|
||||
#define CLKID_VAPB_0 135
|
||||
#define CLKID_VAPB_1_SEL 136
|
||||
#define CLKID_VAPB_1 138
|
||||
#define CLKID_VAPB_SEL 139
|
||||
#define CLKID_VAPB 140
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
#define GPIOAO_11 11
|
||||
#define GPIOAO_12 12
|
||||
#define GPIOAO_13 13
|
||||
#define GPIO_TEST_N 14
|
||||
|
||||
#define GPIOZ_0 0
|
||||
#define GPIOZ_1 1
|
||||
@ -149,6 +150,5 @@
|
||||
#define GPIOCLK_1 116
|
||||
#define GPIOCLK_2 117
|
||||
#define GPIOCLK_3 118
|
||||
#define GPIO_TEST_N 119
|
||||
|
||||
#endif
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#define GPIOAO_7 7
|
||||
#define GPIOAO_8 8
|
||||
#define GPIOAO_9 9
|
||||
#define GPIO_TEST_N 10
|
||||
|
||||
#define GPIOZ_0 0
|
||||
#define GPIOZ_1 1
|
||||
@ -126,6 +127,5 @@
|
||||
#define GPIOX_18 97
|
||||
#define GPIOCLK_0 98
|
||||
#define GPIOCLK_1 99
|
||||
#define GPIO_TEST_N 100
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user