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am33xx: Convert to using <asm/emif.h> to describe the EMIF

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Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2012-05-29 09:02:15 -07:00 committed by Albert ARIBAUD
parent 79b3e6b75b
commit 7d5eb34908
2 changed files with 15 additions and 41 deletions
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29
arch/arm/cpu/armv7/am33xx/ddr.c
View File

@ -18,12 +18,13 @@ http://www.ti.com/
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/io.h>
#include <asm/emif.h>
/**
* Base address for EMIF instances
*/
static struct emif_regs *emif_reg = {
(struct emif_regs *)EMIF4_0_CFG_BASE};
static struct emif_reg_struct *emif_reg = {
(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
/**
* Base address for DDR instance
@ -48,10 +49,10 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
*/
int config_sdram(struct sdram_config *cfg)
{
writel(cfg->sdrcr, &emif_reg->sdrcr);
writel(cfg->sdrcr2, &emif_reg->sdrcr2);
writel(cfg->refresh, &emif_reg->sdrrcr);
writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
writel(cfg->sdrcr2, &emif_reg->emif_lpddr2_nvm_config);
writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
return 0;
}
@ -61,12 +62,12 @@ int config_sdram(struct sdram_config *cfg)
*/
int set_sdram_timings(struct sdram_timing *t)
{
writel(t->time1, &emif_reg->sdrtim1);
writel(t->time1_sh, &emif_reg->sdrtim1sr);
writel(t->time2, &emif_reg->sdrtim2);
writel(t->time2_sh, &emif_reg->sdrtim2sr);
writel(t->time3, &emif_reg->sdrtim3);
writel(t->time3_sh, &emif_reg->sdrtim3sr);
writel(t->time1, &emif_reg->emif_sdram_tim_1);
writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
writel(t->time2, &emif_reg->emif_sdram_tim_2);
writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
writel(t->time3, &emif_reg->emif_sdram_tim_3);
writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
return 0;
}
@ -76,8 +77,8 @@ int set_sdram_timings(struct sdram_timing *t)
*/
int config_ddr_phy(struct ddr_phy_control *p)
{
writel(p->reg, &emif_reg->ddrphycr);
writel(p->reg_sh, &emif_reg->ddrphycsr);
writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
return 0;
}

27
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@ -55,33 +55,6 @@
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_IOCTRL_VALUE 0x18B
/**
* This structure represents the EMIF registers on AM33XX devices.
*/
struct emif_regs {
unsigned int sdrrev; /* offset 0x00 */
unsigned int sdrstat; /* offset 0x04 */
unsigned int sdrcr; /* offset 0x08 */
unsigned int sdrcr2; /* offset 0x0C */
unsigned int sdrrcr; /* offset 0x10 */
unsigned int sdrrcsr; /* offset 0x14 */
unsigned int sdrtim1; /* offset 0x18 */
unsigned int sdrtim1sr; /* offset 0x1C */
unsigned int sdrtim2; /* offset 0x20 */
unsigned int sdrtim2sr; /* offset 0x24 */
unsigned int sdrtim3; /* offset 0x28 */
unsigned int sdrtim3sr; /* offset 0x2C */
unsigned int res1[2];
unsigned int sdrmcr; /* offset 0x38 */
unsigned int sdrmcsr; /* offset 0x3C */
unsigned int res2[8];
unsigned int sdritr; /* offset 0x60 */
unsigned int res3[32];
unsigned int ddrphycr; /* offset 0xE4 */
unsigned int ddrphycsr; /* offset 0xE8 */
unsigned int ddrphycr2; /* offset 0xEC */
};
/**
* Encapsulates DDR PHY control and corresponding shadow registers.
*/