ppc4xx: Minor updates for DU440 boards
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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@ -67,12 +67,12 @@ int board_early_init_f(void)
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out_be32((void*)GPIO1_OR, 0x00000000);
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out_be32((void*)GPIO1_TCR, 0xc2000000 |
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CFG_GPIO1_IORSTN |
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CFG_GPIO1_IORST2N |
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CFG_GPIO1_LEDUSR1 |
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CFG_GPIO1_LEDUSR2 |
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CFG_GPIO1_LEDPOST |
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CFG_GPIO1_LEDDU);
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out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
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out_be32((void*)GPIO1_OSRL, 0x5c280000);
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out_be32((void*)GPIO1_OSRH, 0x00000000);
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out_be32((void*)GPIO1_TSRL, 0x0c000000);
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@ -243,7 +243,8 @@ int misc_init_r(void)
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* release IO-RST#
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* We have to wait at least 560ms until we may call usbhub_init
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*/
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
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CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N);
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/*
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* flash USR1/2 LEDs (600ms)
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@ -24,6 +24,7 @@
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#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
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#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
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#define CFG_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
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#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
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#define CFG_GPIO1_HWVER_SHIFT 4
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@ -157,10 +157,9 @@
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*/
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#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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/* 440EPx errata CHIP 11 */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#if 0
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#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
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#endif
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#define CONFIG_DDR_ECC /* Use ECC when available */
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#define SPD_EEPROM_ADDRESS {0x50}
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#define CONFIG_PROG_SDRAM_TLB
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@ -244,9 +243,6 @@
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"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
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"cp.b 100000 FFFA0000 60000\0" \
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""
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#if 0
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#endif
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#define CONFIG_PREBOOT /* enable preboot variable */
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@ -264,7 +260,7 @@ int du440_phy_addr(int devnum);
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#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_GIGE 1 /* Include GbE detection */
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#undef CONFIG_PHY_GIGE /* no GbE detection */
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#define CONFIG_HAS_ETH0
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#define CFG_RX_ETH_BUFFER 128
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@ -295,7 +291,9 @@ int du440_phy_addr(int devnum);
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#include <config_cmd_default.h>
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#define CONFIG_CMD_AUTOSCRIPT
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_BMP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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@ -431,8 +429,6 @@ int du440_phy_addr(int devnum);
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#if 0
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#define CONFIG_SHOW_ACTIVITY 1
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#endif
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#define CONFIG_AUTOSCRIPT 1
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#endif /* __CONFIG_H */
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