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Convert CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE to Kconfig

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This converts the following to Kconfig:
   CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-07-31 21:08:25 -04:00
parent 8b549c0b23
commit 7ae1e6a3a3
8 changed files with 8 additions and 3 deletions
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1
configs/pico-imx6_defconfig
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@ -72,6 +72,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y

1
configs/warp7_bl33_defconfig
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@ -47,6 +47,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y

1
configs/warp7_defconfig
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@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y

1
configs/warp_defconfig
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@ -41,6 +41,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
CONFIG_FSL_USDHC=y
CONFIG_POWER_LEGACY=y
CONFIG_POWER_I2C=y

4
drivers/mmc/Kconfig
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@ -864,6 +864,10 @@ config FSL_ESDHC_IMX
This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
config SYS_FSL_ESDHC_HAS_DDR_MODE
bool "i.MX eSDHC controller supports DDR mode"
depends on FSL_ESDHC_IMX
config FSL_USDHC
bool "Freescale/NXP i.MX uSDHC controller support"
depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT

1
include/configs/pico-imx6.h
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@ -22,7 +22,6 @@
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

1
include/configs/warp.h
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@ -18,7 +18,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* Watchdog */

1
include/configs/warp7.h
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@ -15,7 +15,6 @@
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \