leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Enable L2 cache for MPC8568MDS board

Browse Source 
The L2 cache size is 512KB for 8568, print out the correct informaiton.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
This commit is contained in:
Haiying Wang 2007-08-23 15:20:54 -04:00 committed by Andrew Fleming-AFLEMING
parent 94c47fdaf1
commit 7a1ac419fa
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
cpu/mpc85xx/cpu_init.c
View File

@ -247,7 +247,7 @@ int cpu_init_r(void)
switch (cache_ctl & 0x30000000) {
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
ver == SVR_8544) {
ver == SVR_8544 || ver == SVR_8568_E) {
printf ("L2 cache 512KB:");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;

6
include/configs/MPC8568MDS.h
View File

@ -63,9 +63,9 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.