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ARM: tegra: Enable SMMU when going non-secure

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Make sure to enable the SMMU when booting the kernel in non-secure mode.
This is necessary because some of the SMMU registers are restricted to
TrustZone-secured requestors, hence the kernel wouldn't be able to turn
the SMMU on. At the same time, enable translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Thierry Reding 2015-04-21 07:18:38 +02:00 committed by Tom Warren
parent a0d0a594cc
commit 79cf644e2d
2 changed files with 42 additions and 0 deletions
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2
arch/arm/include/asm/arch-tegra124/mc.h
View File

@ -74,6 +74,8 @@ struct mc_ctlr {
u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
};
#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)

40
arch/arm/mach-tegra/ap.c
View File

@ -169,6 +169,43 @@ void protect_secure_section(void)
}
#endif
#if defined(CONFIG_ARMV7_NONSEC)
static void smmu_flush(struct mc_ctlr *mc)
{
(void)readl(&mc->mc_smmu_config);
}
static void smmu_enable(void)
{
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
u32 value;
/*
* Enable translation for all clients since access to this register
* is restricted to TrustZone-secured requestors. The kernel will use
* the per-SWGROUP enable bits to enable or disable translations.
*/
writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
/*
* Enable SMMU globally since access to this register is restricted
* to TrustZone-secured requestors.
*/
value = readl(&mc->mc_smmu_config);
value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
writel(value, &mc->mc_smmu_config);
smmu_flush(mc);
}
#else
static void smmu_enable(void)
{
}
#endif
void s_init(void)
{
/* Init PMC scratch memory */
@ -179,6 +216,9 @@ void s_init(void)
/* init the cache */
config_cache();
/* enable SMMU */
smmu_enable();
/* init vpr */
config_vpr();
}