mpc8xx: remove R360MPI board support
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
8737fc7529
commit
79cbecb81b
@ -28,9 +28,6 @@ config TARGET_LWMON
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config TARGET_NETVIA
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bool "Support NETVIA"
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config TARGET_R360MPI
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bool "Support R360MPI"
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config TARGET_TQM823L
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bool "Support TQM823L"
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@ -75,7 +72,6 @@ source "board/ip860/Kconfig"
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source "board/ivm/Kconfig"
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source "board/lwmon/Kconfig"
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source "board/netvia/Kconfig"
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source "board/r360mpi/Kconfig"
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source "board/tqc/tqm8xx/Kconfig"
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endmenu
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@ -129,7 +129,6 @@ void cpu_init_f (volatile immap_t * immr)
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defined(CONFIG_IVML24) || \
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defined(CONFIG_IVMS8) || \
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defined(CONFIG_LWMON) || \
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defined(CONFIG_R360MPI) || \
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defined(CONFIG_RMU)
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memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
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@ -1,9 +0,0 @@
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if TARGET_R360MPI
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config SYS_BOARD
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default "r360mpi"
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config SYS_CONFIG_NAME
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default "R360MPI"
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endif
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@ -1,6 +0,0 @@
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R360MPI BOARD
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M: Wolfgang Denk <wd@denx.de>
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S: Maintained
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F: board/r360mpi/
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F: include/configs/R360MPI.h
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F: configs/R360MPI_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = r360mpi.o flash.o pcmcia.o
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@ -1,468 +0,0 @@
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/*
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* (C) Copyright 2001
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* #define DEBUG */
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#include <common.h>
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#include <mpc8xx.h>
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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#if defined(CONFIG_ENV_IS_IN_FLASH)
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# ifndef CONFIG_ENV_ADDR
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# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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# endif
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# ifndef CONFIG_ENV_SIZE
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# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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# endif
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# ifndef CONFIG_ENV_SECT_SIZE
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# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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# endif
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#endif
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/*-----------------------------------------------------------------------
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* Protection Flags:
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*/
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#define FLAG_PROTECT_SET 0x01
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#define FLAG_PROTECT_CLEAR 0x02
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/* Board support for 1 or 2 flash devices */
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#undef FLASH_PORT_WIDTH32
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#define FLASH_PORT_WIDTH16
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#ifdef FLASH_PORT_WIDTH16
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#define FLASH_PORT_WIDTH ushort
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#define FLASH_PORT_WIDTHV vu_short
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#else
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#define FLASH_PORT_WIDTH ulong
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#define FLASH_PORT_WIDTHV vu_long
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#endif
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (FPW * addr, flash_info_t * info);
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static int write_data (flash_info_t * info, ulong dest, FPW data);
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static void flash_get_offsets (ulong base, flash_info_t * info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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unsigned long size_b0;
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int i;
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/* Init: no FLASHes known */
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0 << 20);
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}
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/* Remap FLASH according to real size */
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memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
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memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
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/* Re-do sizing to get full correct info */
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size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
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flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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/* monitor protection ON by default */
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(void) flash_protect (FLAG_PROTECT_SET,
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CONFIG_SYS_FLASH_BASE,
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CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
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&flash_info[0]);
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#endif
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
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&flash_info[0]);
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#endif
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flash_info[0].size = size_b0;
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return (size_b0);
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t * info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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return;
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}
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] = base + (i * 0x00020000);
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t * info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_INTEL:
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printf ("INTEL ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_28F320J3A:
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printf ("28F320J3A\n");
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break;
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case FLASH_28F640J3A:
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printf ("28F640J3A\n");
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break;
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case FLASH_28F128J3A:
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printf ("28F128J3A\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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return;
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}
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/*-----------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (FPW * addr, flash_info_t * info)
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{
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FPW value;
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/* Make sure Block Lock Bits get cleared */
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addr[0] = (FPW) 0x00FF00FF;
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addr[0] = (FPW) 0x00600060;
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addr[0] = (FPW) 0x00D000D0;
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addr[0] = (FPW) 0x00FF00FF;
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/* Write auto select command: read Manufacturer ID */
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addr[0x5555] = (FPW) 0x00AA00AA;
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addr[0x2AAA] = (FPW) 0x00550055;
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addr[0x5555] = (FPW) 0x00900090;
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value = addr[0];
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debug("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
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switch (value) {
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case (FPW) INTEL_MANUFACT:
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info->flash_id = FLASH_MAN_INTEL;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
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return (0); /* no or unknown flash */
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}
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value = addr[1]; /* device ID */
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debug("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), value);
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switch (value) {
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case (FPW) INTEL_ID_28F320J3A:
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info->flash_id += FLASH_28F320J3A;
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info->sector_count = 32;
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info->size = 0x00400000;
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break; /* => 4 MB */
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case (FPW) INTEL_ID_28F640J3A:
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info->flash_id += FLASH_28F640J3A;
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info->sector_count = 64;
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info->size = 0x00800000;
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break; /* => 8 MB */
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case (FPW) INTEL_ID_28F128J3A:
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info->flash_id += FLASH_28F128J3A;
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info->sector_count = 128;
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info->size = 0x01000000;
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break; /* => 16 MB */
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default:
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info->flash_id = FLASH_UNKNOWN;
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break;
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}
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if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
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printf ("** ERROR: sector count %d > max (%d) **\n",
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info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
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info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
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}
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
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return (info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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int flag, prot, sect;
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ulong type, start, now, last;
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int rcode = 0;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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type = (info->flash_id & FLASH_VENDMASK);
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if ((type != FLASH_MAN_INTEL)) {
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printf ("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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start = get_timer (0);
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last = start;
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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FPWV *addr = (FPWV *) (info->start[sect]);
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FPW status;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts ();
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*addr = (FPW) 0x00500050; /* clear status register */
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*addr = (FPW) 0x00200020; /* erase setup */
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*addr = (FPW) 0x00D000D0; /* erase confirm */
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts ();
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/* wait at least 80us - let's wait 1 ms */
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udelay (1000);
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while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
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if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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*addr = (FPW) 0x00B000B0; /* suspend erase */
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*addr = (FPW) 0x00FF00FF; /* reset to read mode */
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rcode = 1;
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break;
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}
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/* show that we're waiting */
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if ((now - last) > 1000) { /* every second */
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putc ('.');
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last = now;
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}
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}
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*addr = (FPW) 0x00FF00FF; /* reset to read mode */
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}
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}
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printf (" done\n");
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return rcode;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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* 4 - Flash not identified
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*/
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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ulong cp, wp;
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FPW data;
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int i, l, rc, port_width;
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if (info->flash_id == FLASH_UNKNOWN) {
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return 4;
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}
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/* get lower word aligned address */
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#ifdef FLASH_PORT_WIDTH16
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wp = (addr & ~1);
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port_width = 2;
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#else
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wp = (addr & ~3);
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port_width = 4;
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#endif
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i = 0, cp = wp; i < l; ++i, ++cp) {
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data = (data << 8) | (*(uchar *) cp);
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}
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for (; i < port_width && cnt > 0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt == 0 && i < port_width; ++i, ++cp) {
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data = (data << 8) | (*(uchar *) cp);
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}
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if ((rc = write_data (info, wp, data)) != 0) {
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return (rc);
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}
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wp += port_width;
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}
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/*
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* handle word aligned part
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*/
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while (cnt >= port_width) {
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data = 0;
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for (i = 0; i < port_width; ++i) {
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data = (data << 8) | *src++;
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}
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if ((rc = write_data (info, wp, data)) != 0) {
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return (rc);
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}
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wp += port_width;
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cnt -= port_width;
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}
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if (cnt == 0) {
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return (0);
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}
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/*
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* handle unaligned tail bytes
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*/
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data = 0;
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for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
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data = (data << 8) | *src++;
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--cnt;
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}
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for (; i < port_width; ++i, ++cp) {
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data = (data << 8) | (*(uchar *) cp);
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}
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return (write_data (info, wp, data));
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}
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/*-----------------------------------------------------------------------
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* Write a word or halfword to Flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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static int write_data (flash_info_t * info, ulong dest, FPW data)
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{
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FPWV *addr = (FPWV *) dest;
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ulong status;
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ulong start;
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int flag;
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/* Check if Flash is (sufficiently) erased */
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if ((*addr & data) != data) {
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printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
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return (2);
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}
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts ();
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*addr = (FPW) 0x00400040; /* write setup */
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*addr = data;
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||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
start = get_timer (0);
|
||||
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -1,232 +0,0 @@
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
#include <pcmcia.h>
|
||||
|
||||
#undef CONFIG_PCMCIA
|
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA)
|
||||
#define CONFIG_PCMCIA
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
|
||||
#define CONFIG_PCMCIA
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCMCIA
|
||||
|
||||
#define PCMCIA_BOARD_MSG "R360MPI"
|
||||
|
||||
int pcmcia_hardware_enable(int slot)
|
||||
{
|
||||
volatile immap_t *immap;
|
||||
volatile pcmconf8xx_t *pcmp;
|
||||
volatile sysconf8xx_t *sysp;
|
||||
uint reg, mask;
|
||||
|
||||
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
|
||||
|
||||
/*
|
||||
* Configure SIUMCR to enable PCMCIA port B
|
||||
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
|
||||
*/
|
||||
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
|
||||
|
||||
/* clear interrupt state, and disable interrupts */
|
||||
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
|
||||
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
|
||||
|
||||
/*
|
||||
* Disable interrupts, DMA, and PCMCIA buffers
|
||||
* (isolate the interface) and assert RESET signal
|
||||
*/
|
||||
debug ("Disable PCMCIA buffers and assert RESET\n");
|
||||
reg = 0;
|
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
udelay(500);
|
||||
|
||||
/*
|
||||
* Configure Ports A, B & C pins for
|
||||
* 5 Volts Enable and 3 Volts enable
|
||||
*/
|
||||
immap->im_ioport.iop_pcpar &= ~(0x0400);
|
||||
immap->im_ioport.iop_pcso &= ~(0x0400);/*
|
||||
immap->im_ioport.iop_pcdir |= 0x0400;*/
|
||||
|
||||
immap->im_ioport.iop_papar &= ~(0x0200);/*
|
||||
immap->im_ioport.iop_padir |= 0x0200;*/
|
||||
#if 0
|
||||
immap->im_ioport.iop_pbpar &= ~(0xC000);
|
||||
immap->im_ioport.iop_pbdir &= ~(0xC000);
|
||||
#endif
|
||||
/* remove all power */
|
||||
|
||||
immap->im_ioport.iop_pcdat |= 0x0400;
|
||||
immap->im_ioport.iop_padat |= 0x0200;
|
||||
|
||||
/*
|
||||
* Make sure there is a card in the slot, then configure the interface.
|
||||
*/
|
||||
udelay(10000);
|
||||
debug ("[%d] %s: PIPR(%p)=0x%x\n",
|
||||
__LINE__,__FUNCTION__,
|
||||
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
|
||||
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
|
||||
printf (" No Card found\n");
|
||||
return (1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Power On.
|
||||
*/
|
||||
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
|
||||
reg = pcmp->pcmc_pipr;
|
||||
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
|
||||
reg,
|
||||
(reg&PCMCIA_VS1(slot))?"n":"ff",
|
||||
(reg&PCMCIA_VS2(slot))?"n":"ff");
|
||||
if ((reg & mask) == mask) {
|
||||
immap->im_ioport.iop_pcdat &= ~(0x4000);
|
||||
puts (" 5.0V card found: ");
|
||||
} else {
|
||||
immap->im_ioport.iop_padat &= ~(0x0002);
|
||||
puts (" 3.3V card found: ");
|
||||
}
|
||||
immap->im_ioport.iop_pcdir |= 0x0400;
|
||||
immap->im_ioport.iop_padir |= 0x0200;
|
||||
#if 0
|
||||
/* VCC switch error flag, PCMCIA slot INPACK_ pin */
|
||||
cp->cp_pbdir &= ~(0x0020 | 0x0010);
|
||||
cp->cp_pbpar &= ~(0x0020 | 0x0010);
|
||||
udelay(500000);
|
||||
#endif
|
||||
debug ("Enable PCMCIA buffers and stop RESET\n");
|
||||
reg = PCMCIA_PGCRX(_slot_);
|
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
|
||||
udelay(250000); /* some cards need >150 ms to come up :-( */
|
||||
|
||||
debug ("# hardware_enable done\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA)
|
||||
int pcmcia_hardware_disable(int slot)
|
||||
{
|
||||
volatile immap_t *immap;
|
||||
u_long reg;
|
||||
|
||||
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
|
||||
|
||||
immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
|
||||
/* remove all power */
|
||||
immap->im_ioport.iop_pcdat |= 0x0400;
|
||||
immap->im_ioport.iop_padat |= 0x0200;
|
||||
|
||||
/* Configure PCMCIA General Control Register */
|
||||
debug ("Disable PCMCIA buffers and assert RESET\n");
|
||||
reg = 0;
|
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
|
||||
udelay(10000);
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
int pcmcia_voltage_set(int slot, int vcc, int vpp)
|
||||
{
|
||||
volatile immap_t *immap;
|
||||
volatile pcmconf8xx_t *pcmp;
|
||||
u_long reg;
|
||||
|
||||
debug ("voltage_set: "
|
||||
PCMCIA_BOARD_MSG
|
||||
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
|
||||
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
|
||||
|
||||
immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
|
||||
/*
|
||||
* Disable PCMCIA buffers (isolate the interface)
|
||||
* and assert RESET signal
|
||||
*/
|
||||
debug ("Disable PCMCIA buffers and assert RESET\n");
|
||||
reg = PCMCIA_PGCRX(_slot_);
|
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
udelay(500);
|
||||
|
||||
/*
|
||||
* Configure Ports A & C pins for
|
||||
* 5 Volts Enable and 3 Volts enable,
|
||||
* Turn off all power
|
||||
*/
|
||||
debug ("PCMCIA power OFF\n");
|
||||
immap->im_ioport.iop_pcpar &= ~(0x0400);
|
||||
immap->im_ioport.iop_pcso &= ~(0x0400);/*
|
||||
immap->im_ioport.iop_pcdir |= 0x0400;*/
|
||||
|
||||
immap->im_ioport.iop_papar &= ~(0x0200);/*
|
||||
immap->im_ioport.iop_padir |= 0x0200;*/
|
||||
|
||||
immap->im_ioport.iop_pcdat |= 0x0400;
|
||||
immap->im_ioport.iop_padat |= 0x0200;
|
||||
|
||||
reg = 0;
|
||||
switch(vcc) {
|
||||
case 0: break;
|
||||
case 33: reg |= 0x0200; break;
|
||||
case 50: reg |= 0x0400; break;
|
||||
default: goto done;
|
||||
}
|
||||
|
||||
/* Checking supported voltages */
|
||||
|
||||
debug ("PIPR: 0x%x --> %s\n",
|
||||
pcmp->pcmc_pipr,
|
||||
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
|
||||
|
||||
if (reg & 0x0200)
|
||||
immap->im_ioport.iop_pcdat &= !reg;
|
||||
if (reg & 0x0400)
|
||||
immap->im_ioport.iop_padat &= !reg;
|
||||
immap->im_ioport.iop_pcdir |= 0x0200;
|
||||
immap->im_ioport.iop_padir |= 0x0400;
|
||||
if (reg) {
|
||||
debug ("PCMCIA powered at %sV\n",
|
||||
(reg&0x0400) ? "5.0" : "3.3");
|
||||
} else {
|
||||
debug ("PCMCIA powered down\n");
|
||||
}
|
||||
|
||||
done:
|
||||
debug ("Enable PCMCIA buffers and stop RESET\n");
|
||||
reg = PCMCIA_PGCRX(_slot_);
|
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
udelay(500);
|
||||
|
||||
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
|
||||
slot+'A');
|
||||
return (0);
|
||||
}
|
||||
|
||||
#endif /* CCONFIG_PCMCIA */
|
||||
@ -1,403 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2001-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <mpc8xx.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#include <commproc.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h> /* for strdup */
|
||||
|
||||
|
||||
/*
|
||||
* Memory Controller Using
|
||||
*
|
||||
* CS0 - Flash memory (0x40000000)
|
||||
* CS1 - FLASH memory (0x????????)
|
||||
* CS2 - SDRAM (0x00000000)
|
||||
* CS3 -
|
||||
* CS4 -
|
||||
* CS5 -
|
||||
* CS6 - PCMCIA device
|
||||
* CS7 - PCMCIA device
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define _not_used_ 0xffffffff
|
||||
|
||||
const uint sdram_table[]=
|
||||
{
|
||||
/* single read. (offset 0 in upm RAM) */
|
||||
0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
|
||||
0x1ff77c47,
|
||||
|
||||
/* MRS initialization (offset 5) */
|
||||
|
||||
0x1ff77c34, 0xefeabc34, 0x1fb57c35,
|
||||
|
||||
/* burst read. (offset 8 in upm RAM) */
|
||||
0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
|
||||
0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
|
||||
_not_used_, _not_used_, _not_used_, _not_used_,
|
||||
_not_used_, _not_used_, _not_used_, _not_used_,
|
||||
|
||||
/* single write. (offset 18 in upm RAM) */
|
||||
0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
|
||||
_not_used_, _not_used_, _not_used_, _not_used_,
|
||||
|
||||
/* burst write. (offset 20 in upm RAM) */
|
||||
0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
|
||||
0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
|
||||
_not_used_, _not_used_, _not_used_, _not_used_,
|
||||
_not_used_, _not_used_, _not_used_, _not_used_,
|
||||
|
||||
/* refresh. (offset 30 in upm RAM) */
|
||||
0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
|
||||
0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
|
||||
_not_used_, _not_used_, _not_used_, _not_used_,
|
||||
|
||||
/* exception. (offset 3c in upm RAM) */
|
||||
0x7ffffc07, _not_used_, _not_used_, _not_used_ };
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: R360 MPI Board\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static long int dram_size (long int, long int *, long int);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
long int size8, size9;
|
||||
long int size_b0 = 0;
|
||||
unsigned long reg;
|
||||
|
||||
upmconfig (UPMA, (uint *) sdram_table,
|
||||
sizeof (sdram_table) / sizeof (uint));
|
||||
|
||||
/*
|
||||
* Preliminary prescaler for refresh (depends on number of
|
||||
* banks): This value is selected for four cycles every 62.4 us
|
||||
* with two SDRAM banks or four cycles every 31.2 us with one
|
||||
* bank. It will be adjusted after memory sizing.
|
||||
*/
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
|
||||
|
||||
memctl->memc_mar = 0x00000088;
|
||||
|
||||
/*
|
||||
* Map controller bank 2 to the SDRAM bank at
|
||||
* preliminary address - these have to be modified after the
|
||||
* SDRAM size has been determined.
|
||||
*/
|
||||
memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
|
||||
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
|
||||
|
||||
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
|
||||
|
||||
udelay (200);
|
||||
|
||||
/* perform SDRAM initializsation sequence */
|
||||
|
||||
memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
|
||||
udelay (200);
|
||||
memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
|
||||
udelay (200);
|
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
|
||||
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* Check Bank 2 Memory Size for re-configuration
|
||||
*
|
||||
* try 8 column mode
|
||||
*/
|
||||
size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
|
||||
SDRAM_MAX_SIZE);
|
||||
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* try 9 column mode
|
||||
*/
|
||||
size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
|
||||
SDRAM_MAX_SIZE);
|
||||
|
||||
if (size8 < size9) { /* leave configuration at 9 columns */
|
||||
size_b0 = size9;
|
||||
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
|
||||
} else { /* back to 8 columns */
|
||||
size_b0 = size8;
|
||||
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
|
||||
udelay (500);
|
||||
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
|
||||
}
|
||||
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* Adjust refresh rate depending on SDRAM type, both banks
|
||||
* For types > 128 MBit leave it at the current (fast) rate
|
||||
*/
|
||||
if ((size_b0 < 0x02000000)) {
|
||||
/* reduce to 15.6 us (62.4 us / quad) */
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
|
||||
udelay (1000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Final mapping
|
||||
*/
|
||||
|
||||
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
|
||||
memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
|
||||
|
||||
/* adjust refresh rate depending on SDRAM type, one bank */
|
||||
reg = memctl->memc_mptpr;
|
||||
reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
|
||||
memctl->memc_mptpr = reg;
|
||||
|
||||
udelay (10000);
|
||||
|
||||
#ifdef CONFIG_CAN_DRIVER
|
||||
/* Initialize OR3 / BR3 */
|
||||
memctl->memc_or3 = CONFIG_SYS_OR3_CAN; /* switch GPLB_5 to GPLA_5 */
|
||||
memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
|
||||
|
||||
/* Initialize MBMR */
|
||||
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
|
||||
|
||||
/* Initialize UPMB for CAN: single read */
|
||||
memctl->memc_mdr = 0xFFFFC004;
|
||||
memctl->memc_mcr = 0x0100 | UPMB;
|
||||
|
||||
memctl->memc_mdr = 0x0FFFD004;
|
||||
memctl->memc_mcr = 0x0101 | UPMB;
|
||||
|
||||
memctl->memc_mdr = 0x0FFFC000;
|
||||
memctl->memc_mcr = 0x0102 | UPMB;
|
||||
|
||||
memctl->memc_mdr = 0x3FFFC004;
|
||||
memctl->memc_mcr = 0x0103 | UPMB;
|
||||
|
||||
memctl->memc_mdr = 0xFFFFDC05;
|
||||
memctl->memc_mcr = 0x0104 | UPMB;
|
||||
|
||||
/* Initialize UPMB for CAN: single write */
|
||||
memctl->memc_mdr = 0xFFFCC004;
|
||||
memctl->memc_mcr = 0x0118 | UPMB;
|
||||
|
||||
memctl->memc_mdr = 0xCFFCD004;
|
||||
memctl->memc_mcr = 0x0119 | UPMB;
|
||||
|
||||
memctl->memc_mdr = 0x0FFCC000;
|
||||
memctl->memc_mcr = 0x011A | UPMB;
|
||||
|
||||
memctl->memc_mdr = 0x7FFCC004;
|
||||
memctl->memc_mcr = 0x011B | UPMB;
|
||||
|
||||
memctl->memc_mdr = 0xFFFDCC05;
|
||||
memctl->memc_mcr = 0x011C | UPMB;
|
||||
#endif
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
|
||||
static long int dram_size (long int mamr_value,
|
||||
long int *base, long int maxsize)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
memctl->memc_mamr = mamr_value;
|
||||
|
||||
return (get_ram_size(base, maxsize));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
void r360_i2c_lcd_write (uchar data0, uchar data1)
|
||||
{
|
||||
if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
|
||||
printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
|
||||
}
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Keyboard Controller
|
||||
*/
|
||||
|
||||
/* Number of bytes returned from Keyboard Controller */
|
||||
#define KEYBD_KEY_MAX 16 /* maximum key number */
|
||||
#define KEYBD_DATALEN ((KEYBD_KEY_MAX + 7) / 8) /* normal key scan data */
|
||||
|
||||
static uchar *key_match (uchar *);
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
char kbd_data[KEYBD_DATALEN];
|
||||
char keybd_env[2 * KEYBD_DATALEN + 1];
|
||||
char *str;
|
||||
int i;
|
||||
|
||||
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
|
||||
|
||||
for (i = 0; i < KEYBD_DATALEN; ++i) {
|
||||
sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
|
||||
}
|
||||
setenv ("keybd", keybd_env);
|
||||
|
||||
str = strdup ((char *)key_match ((uchar *)keybd_env)); /* decode keys */
|
||||
|
||||
#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
|
||||
setenv ("preboot", str); /* set or delete definition */
|
||||
#endif /* CONFIG_PREBOOT */
|
||||
if (str != NULL) {
|
||||
free (str);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Check if pressed key(s) match magic sequence,
|
||||
* and return the command string associated with that key(s).
|
||||
*
|
||||
* If no key press was decoded, NULL is returned.
|
||||
*
|
||||
* Note: the first character of the argument will be overwritten with
|
||||
* the "magic charcter code" of the decoded key(s), or '\0'.
|
||||
*
|
||||
*
|
||||
* Note: the string points to static environment data and must be
|
||||
* saved before you call any function that modifies the environment.
|
||||
*/
|
||||
#ifdef CONFIG_PREBOOT
|
||||
|
||||
static uchar kbd_magic_prefix[] = "key_magic";
|
||||
static uchar kbd_command_prefix[] = "key_cmd";
|
||||
|
||||
static uchar *key_match (uchar * kbd_str)
|
||||
{
|
||||
uchar magic[sizeof (kbd_magic_prefix) + 1];
|
||||
uchar cmd_name[sizeof (kbd_command_prefix) + 1];
|
||||
uchar *str, *suffix;
|
||||
uchar *kbd_magic_keys;
|
||||
char *cmd;
|
||||
|
||||
/*
|
||||
* The following string defines the characters that can pe appended
|
||||
* to "key_magic" to form the names of environment variables that
|
||||
* hold "magic" key codes, i. e. such key codes that can cause
|
||||
* pre-boot actions. If the string is empty (""), then only
|
||||
* "key_magic" is checked (old behaviour); the string "125" causes
|
||||
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
|
||||
*/
|
||||
if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
|
||||
/* loop over all magic keys;
|
||||
* use '\0' suffix in case of empty string
|
||||
*/
|
||||
for (suffix = kbd_magic_keys;
|
||||
*suffix || suffix == kbd_magic_keys;
|
||||
++suffix) {
|
||||
sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix);
|
||||
|
||||
#if 0
|
||||
printf ("### Check magic \"%s\"\n", magic);
|
||||
#endif
|
||||
|
||||
if ((str = (uchar *)getenv ((char *)magic)) != 0) {
|
||||
|
||||
#if 0
|
||||
printf ("### Compare \"%s\" \"%s\"\n",
|
||||
kbd_str, str);
|
||||
#endif
|
||||
if (strcmp ((char *)kbd_str, (char *)str) == 0) {
|
||||
sprintf ((char *)cmd_name, "%s%c",
|
||||
kbd_command_prefix,
|
||||
*suffix);
|
||||
|
||||
if ((cmd = getenv ((char *)cmd_name)) != 0) {
|
||||
#if 0
|
||||
printf ("### Set PREBOOT to $(%s): \"%s\"\n",
|
||||
cmd_name, cmd);
|
||||
#endif
|
||||
return ((uchar *)cmd);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
printf ("### Delete PREBOOT\n");
|
||||
#endif
|
||||
*kbd_str = '\0';
|
||||
return (NULL);
|
||||
}
|
||||
#endif /* CONFIG_PREBOOT */
|
||||
|
||||
/* Read Keyboard status */
|
||||
int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
uchar kbd_data[KEYBD_DATALEN];
|
||||
uchar keybd_env[2 * KEYBD_DATALEN + 1];
|
||||
int i;
|
||||
|
||||
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
/* Read keys */
|
||||
i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
|
||||
|
||||
puts ("Keys:");
|
||||
for (i = 0; i < KEYBD_DATALEN; ++i) {
|
||||
sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
|
||||
printf (" %02x", kbd_data[i]);
|
||||
}
|
||||
putc ('\n');
|
||||
setenv ("keybd", (char *)keybd_env);
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
kbd, 1, 1, do_kbd,
|
||||
"read keyboard status",
|
||||
""
|
||||
);
|
||||
@ -1,89 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
. = ALIGN(128 * 1024);
|
||||
.ppcenv :
|
||||
{
|
||||
common/env_embedded.o (.ppcenv)
|
||||
}
|
||||
}
|
||||
@ -1,3 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_8xx=y
|
||||
CONFIG_TARGET_R360MPI=y
|
||||
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
||||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
|
||||
RRvision powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
|
||||
SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
|
||||
KUP4K powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
|
||||
|
||||
@ -423,31 +423,6 @@ void lcd_enable (void)
|
||||
pic_write (0x60, c);
|
||||
}
|
||||
#endif /* CONFIG_LWMON */
|
||||
|
||||
#if defined(CONFIG_R360MPI)
|
||||
{
|
||||
extern void r360_i2c_lcd_write (uchar data0, uchar data1);
|
||||
unsigned long bgi, ctr;
|
||||
char *p;
|
||||
|
||||
if ((p = getenv("lcdbgi")) != NULL) {
|
||||
bgi = simple_strtoul (p, 0, 10) & 0xFFF;
|
||||
} else {
|
||||
bgi = 0xFFF;
|
||||
}
|
||||
|
||||
if ((p = getenv("lcdctr")) != NULL) {
|
||||
ctr = simple_strtoul (p, 0, 10) & 0xFFF;
|
||||
} else {
|
||||
ctr=0x7FF;
|
||||
}
|
||||
|
||||
r360_i2c_lcd_write(0x10, 0x01);
|
||||
r360_i2c_lcd_write(0x20, 0x01);
|
||||
r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
|
||||
r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
|
||||
}
|
||||
#endif /* CONFIG_R360MPI */
|
||||
}
|
||||
|
||||
/************************************************************************/
|
||||
|
||||
@ -630,7 +630,6 @@ typedef struct scc_enet {
|
||||
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
|
||||
|
||||
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
|
||||
defined(CONFIG_R360MPI) || \
|
||||
defined(CONFIG_TQM823L) || \
|
||||
defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
|
||||
defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D)
|
||||
@ -650,9 +649,6 @@ typedef struct scc_enet {
|
||||
|
||||
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
|
||||
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
|
||||
#if defined(CONFIG_R360MPI)
|
||||
#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
|
||||
#endif /* CONFIG_R360MPI */
|
||||
|
||||
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
|
||||
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
|
||||
|
||||
@ -1,464 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
|
||||
#define CONFIG_R360MPI 1
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000
|
||||
|
||||
#define CONFIG_LCD
|
||||
#define CONFIG_MPC8XX_LCD
|
||||
#undef CONFIG_EDT32F10
|
||||
#define CONFIG_SHARP_LQ057Q3DC02
|
||||
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
|
||||
#define MPC8XX_FACT 1 /* Multiply by 1 */
|
||||
#define MPC8XX_XIN 50000000 /* 50 MHz in */
|
||||
#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY 0 /* immediate boot */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
|
||||
"bootm"
|
||||
|
||||
#undef CONFIG_SCC1_ENET
|
||||
#define CONFIG_SCC2_ENET
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
|
||||
|
||||
#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
|
||||
#undef CONFIG_SYS_I2C_SOFT /* To I2C with software support */
|
||||
#define CONFIG_SYS_I2C_SPEED 4700 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#if defined(CONFIG_SYS_I2C_SOFT)
|
||||
#define CONFIG_SYS_SYS_I2C_SOFT_SPEED 4700 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define PB_SCL 0x00000020 /* PB 26 */
|
||||
#define PB_SDA 0x00000010 /* PB 27 */
|
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
|
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
|
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
|
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
|
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA
|
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL
|
||||
#define I2C_DELAY udelay(50)
|
||||
#endif /* #define(CONFIG_SYS_I2C_SOFT) */
|
||||
|
||||
#define CONFIG_SYS_I2C_LCD_ADDR 0x8 /* LCD Control */
|
||||
#define CONFIG_SYS_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
|
||||
#define CONFIG_SYS_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PCMCIA
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* we need the null device */
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* must set console from env */
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*/
|
||||
/* No command line, one static partition
|
||||
* use all the space starting at offset 3MB*/
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00300000
|
||||
|
||||
/* mtdparts command line support */
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=r360-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)"
|
||||
*/
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFF000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000
|
||||
#if defined(DEBUG)
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#endif
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
|
||||
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CONFIG_SYS_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 50 MHz we use a 1:1 clock */
|
||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#if 1
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
|
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
|
||||
|
||||
/*
|
||||
* BR2 and OR2 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
|
||||
|
||||
#define CONFIG_SYS_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_ACS_DIV1 | OR_CSNT_SAM | \
|
||||
OR_SCY_0_CLK | OR_G5LS)
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR2_AM | CONFIG_SYS_OR_TIMING_SDRAM )
|
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
/*
|
||||
* BR3 and OR3 (CAN Controller)
|
||||
*/
|
||||
#ifdef CONFIG_CAN_DRIVER
|
||||
#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN base address */
|
||||
#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
|
||||
#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA |OR_BI)
|
||||
#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
|
||||
BR_PS_8 | BR_MS_UPMB | BR_V)
|
||||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*
|
||||
* The Divider for PTA (refresh timer) configuration is based on an
|
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to
|
||||
* the number of chip selects (NCS) and the actually needed refresh
|
||||
* rate is done by setting MPTPR.
|
||||
*
|
||||
* PTA is calculated from
|
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock!)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
* --------------------------------------------
|
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
|
||||
*
|
||||
* 50 MHz => 50.000.000 / Divider = 98
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CONFIG_SYS_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CONFIG_SYS_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CONFIG_SYS_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
* (= 64 ms / 2K = 125 / quad bursts).
|
||||
* For a simpler initialization, 15.6 us is used instead.
|
||||
*
|
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
|
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
|
||||
*/
|
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -27,8 +27,6 @@
|
||||
# define CONFIG_PCMCIA_SLOT_A
|
||||
#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
|
||||
# define CONFIG_PCMCIA_SLOT_B
|
||||
#elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
|
||||
# define CONFIG_PCMCIA_SLOT_B
|
||||
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
|
||||
# define CONFIG_PCMCIA_SLOT_A
|
||||
#else
|
||||
|
||||
Loading…
Reference in New Issue
Block a user