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gpio: stm32f7: replace ODR update by BSRR write

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Replace clrsetbits on ODR register (2 operations: one read + one write)
by writing on the correct bit (SET or RESET) of the BSRR register
(only 1 write operation).

Moreover this register if safe for simultaneous access by 2 master on
the bus.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard 2018-08-09 11:57:57 +02:00 committed by Tom Rini
parent c8e570167f
commit 798cd708d5
1 changed files with 5 additions and 6 deletions
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11
drivers/gpio/stm32f7_gpio.c
View File

@ -18,7 +18,7 @@
#define STM32_GPIOS_PER_BANK 16
#define MODE_BITS(gpio_pin) (gpio_pin * 2)
#define MODE_BITS_MASK 3
#define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin))
#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
@ -41,8 +41,8 @@ static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
int mask = MODE_BITS_MASK << bits_index;
clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
mask = IN_OUT_BIT_INDEX(offset);
clrsetbits_le32(&regs->odr, mask, value ? mask : 0);
writel(BSRR_BIT(offset, value), &regs->bsrr);
return 0;
}
@ -52,16 +52,15 @@ static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
return readl(&regs->idr) & IN_OUT_BIT_INDEX(offset) ? 1 : 0;
return readl(&regs->idr) & BIT(offset) ? 1 : 0;
}
static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int mask = IN_OUT_BIT_INDEX(offset);
clrsetbits_le32(&regs->odr, mask, value ? mask : 0);
writel(BSRR_BIT(offset, value), &regs->bsrr);
return 0;
}