clk: sunxi: Add Allwinner R40 CLK driver
Add initial clock driver for Allwinner R40. - Implement USB bus and USB clocks via ccu_clk_gate for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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@ -44,6 +44,13 @@ config CLK_SUN8I_A83T
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This enables common clock driver support for platforms based
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on Allwinner A83T SoC.
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config CLK_SUN8I_R40
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bool "Clock driver for Allwinner R40"
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default MACH_SUN8I_R40
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help
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This enables common clock driver support for platforms based
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on Allwinner R40 SoC.
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config CLK_SUN8I_H3
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bool "Clock driver for Allwinner H3/H5"
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default MACH_SUNXI_H3_H5
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@ -11,5 +11,6 @@ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
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obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
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obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
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obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
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obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
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obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
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obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
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70
drivers/clk/sunxi/clk_r40.c
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70
drivers/clk/sunxi/clk_r40.c
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@ -0,0 +1,70 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/arch/ccu.h>
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#include <dt-bindings/clock/sun8i-r40-ccu.h>
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#include <dt-bindings/reset/sun8i-r40-ccu.h>
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static struct ccu_clk_gate r40_gates[] = {
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[CLK_BUS_OTG] = GATE(0x060, BIT(25)),
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[CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
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[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
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[CLK_BUS_EHCI2] = GATE(0x060, BIT(28)),
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[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
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[CLK_BUS_OHCI1] = GATE(0x060, BIT(30)),
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[CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
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[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
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[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
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[CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
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[CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
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[CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
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[CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
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};
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static struct ccu_reset r40_resets[] = {
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[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
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[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
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[RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
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[RST_BUS_OTG] = RESET(0x2c0, BIT(25)),
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[RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
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[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
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[RST_BUS_EHCI2] = RESET(0x2c0, BIT(28)),
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[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
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[RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
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[RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
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};
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static const struct ccu_desc r40_ccu_desc = {
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.gates = r40_gates,
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.resets = r40_resets,
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};
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static int r40_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets));
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}
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static const struct udevice_id r40_clk_ids[] = {
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{ .compatible = "allwinner,sun8i-r40-ccu",
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.data = (ulong)&r40_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun8i_r40) = {
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.name = "sun8i_r40_ccu",
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.id = UCLASS_CLK,
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.of_match = r40_clk_ids,
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.priv_auto_alloc_size = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = r40_clk_bind,
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};
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