arm: Kirkwood: arch specific updated for ehci-Kirkwood driver support
This patch abstracts Kirkwood arch specific changes to support ehci-kirkwood driver Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
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@ -74,7 +74,7 @@ unsigned char get_random_hex(void)
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* 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
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* NOTE: A value of 0x0 specifies 64-KByte size.
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*/
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static unsigned int kw_winctrl_calcsize(unsigned int sizeval)
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unsigned int kw_winctrl_calcsize(unsigned int sizeval)
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{
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int i;
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unsigned int j = 0;
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@ -87,10 +87,6 @@ static unsigned int kw_winctrl_calcsize(unsigned int sizeval)
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return (0x0000ffff & j);
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}
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/* prepares data to be loaded in win_Ctrl register */
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#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
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| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
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/*
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* kw_config_adr_windows - Configure address Windows
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*
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@ -29,6 +29,9 @@
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#ifndef __ASSEMBLY__
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#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
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| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
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#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
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((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
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@ -57,6 +60,10 @@ enum kwcpu_target {
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enum kwcpu_attrib {
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KWCPU_ATTR_SASRAM = 0x01,
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KWCPU_ATTR_DRAM_CS0 = 0x0e,
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KWCPU_ATTR_DRAM_CS1 = 0x0d,
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KWCPU_ATTR_DRAM_CS2 = 0x0b,
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KWCPU_ATTR_DRAM_CS3 = 0x07,
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KWCPU_ATTR_NANDFLASH = 0x2f,
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KWCPU_ATTR_SPIFLASH = 0x1e,
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KWCPU_ATTR_BOOTROM = 0x1d,
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@ -155,5 +162,6 @@ int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
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unsigned int mpp16_23, unsigned int mpp24_31,
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unsigned int mpp32_39, unsigned int mpp40_47,
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unsigned int mpp48_55);
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unsigned int kw_winctrl_calcsize(unsigned int sizeval);
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#endif /* __ASSEMBLY__ */
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#endif /* _KWCPU_H */
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@ -55,6 +55,7 @@
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#define KW_CPU_REG_BASE (KW_REGISTER(0x20100))
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#define KW_TIMER_BASE (KW_REGISTER(0x20300))
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#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))
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#define KW_USB20_BASE (KW_REGISTER(0x50000))
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#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
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#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
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