XPedite5200 board support
Initial support for Extreme Engineering Solutions XPedite5200 - a MPC8548-based PMC single board computer. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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@ -413,6 +413,7 @@ Rune Torgersen <runet@innovsys.com>
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Peter Tyser <ptyser@xes-inc.com>
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XPEDITE5200 MPC8548
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XPEDITE5370 MPC8572
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David Updegraff <dave@cray.com>
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1
MAKEALL
1
MAKEALL
@ -385,6 +385,7 @@ LIST_85xx=" \
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TQM8548 \
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TQM8555 \
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TQM8560 \
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XPEDITE5200 \
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XPEDITE5370 \
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"
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3
Makefile
3
Makefile
@ -2463,6 +2463,9 @@ TQM8560_config: unconfig
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echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
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@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
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XPEDITE5200_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
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XPEDITE5370_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
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@ -29,9 +29,10 @@ endif
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LIB = $(obj)lib$(VENDOR).a
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COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
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COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o
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COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o
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COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
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COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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@ -34,6 +34,9 @@ extern void fsl_pci_init(struct pci_controller *hose);
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int first_free_busno = 0;
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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@ -44,6 +47,7 @@ static struct pci_controller pcie2_hose;
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static struct pci_controller pcie3_hose;
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#endif
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#ifdef CONFIG_MPC8572
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/* Correlate host/agent POR bits to usable info. Table 4-14 */
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struct host_agent_cfg_t {
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uchar pcie_root[3];
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@ -81,6 +85,38 @@ struct io_port_cfg_t {
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{{0, 0, 0}, 4},
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{{8, 0, 0}, 0},
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};
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#elif defined CONFIG_MPC8548
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/* Correlate host/agent POR bits to usable info. Table 4-12 */
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struct host_agent_cfg_t {
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uchar pci_host[2];
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uchar pcie_root[1];
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uchar rio_host;
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} host_agent_cfg[8] = {
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{{1, 1}, {0}, 0},
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{{1, 1}, {1}, 0},
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{{1, 1}, {0}, 1},
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{{0, 0}, {0}, 0}, /* reserved */
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{{0, 1}, {1}, 0},
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{{1, 1}, {1}, 0},
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{{0, 1}, {1}, 1},
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{{1, 1}, {1}, 1}
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};
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/* Correlate port width POR bits to usable info. Table 4-13 */
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struct io_port_cfg_t {
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uchar pcie_width[1];
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uchar rio_width;
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} io_port_cfg[8] = {
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{{0}, 0},
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{{0}, 0},
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{{0}, 0},
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{{4}, 4},
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{{4}, 4},
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{{0}, 4},
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{{0}, 4},
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{{8}, 0},
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};
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#endif
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void pci_init_board(void)
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{
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@ -94,9 +130,65 @@ void pci_init_board(void)
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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struct pci_region *r;
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debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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#ifdef CONFIG_PCI1
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uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
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uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
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uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
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width = 0; /* Silence compiler warning... */
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io_sel &= 0xf; /* Silence compiler warning... */
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
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hose = &pci1_hose;
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host = host_agent_cfg[host_agent].pci_host[0];
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r = hose->regions;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
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pci_32 ? 32 : 64,
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pcix ? "PCIX" : "PCI",
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pci_spd_norm ? ">=" : "<=",
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pcix ? freq * 2 : freq,
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host ? "host" : "agent",
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pci_arb ? "arbiter" : "external-arbiter");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCI1_MEM_BASE,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCI1_IO_BASE,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int)&pci->cfg_addr,
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(int)&pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno = hose->last_busno+1;
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printf(" PCI1 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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} else {
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printf(" PCI1: disabled\n");
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}
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#elif defined CONFIG_MPC8548
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/* PCI1 not present on MPC8572 */
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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hose = &pcie1_hose;
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@ -143,7 +235,7 @@ void pci_init_board(void)
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno+1;
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first_free_busno = hose->last_busno + 1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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}
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@ -200,7 +292,6 @@ void pci_init_board(void)
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first_free_busno = hose->last_busno+1;
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printf(" PCIE2 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
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@ -267,6 +358,10 @@ extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
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void ft_board_pci_setup(void *blob, bd_t *bd)
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{
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/* TODO - make node name (eg pci0) dynamic */
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#ifdef CONFIG_PCI1
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ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
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#endif
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#ifdef CONFIG_PCIE1
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ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
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#endif
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