MC13892: Add REGMODE0 bits definitions
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
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@ -139,6 +139,22 @@
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#define VCAM_3_0 (3 << 16)
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#define VCAM_MASK (3 << 16)
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/* Reg Mode 0 */
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#define VGEN1EN (1 << 0)
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#define VGEN1STBY (1 << 1)
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#define VGEN1MODE (1 << 2)
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#define VIOHIEN (1 << 3)
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#define VIOHISTBY (1 << 4)
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#define VDIGEN (1 << 9)
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#define VDIGSTBY (1 << 10)
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#define VGEN2EN (1 << 12)
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#define VGEN2STBY (1 << 13)
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#define VGEN2MODE (1 << 14)
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#define VPLLEN (1 << 15)
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#define VPLLSTBY (1 << 16)
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#define VUSBEN (1 << 18)
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#define VUSBSTBY (1 << 19)
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/* Reg Mode 1 */
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#define VGEN3EN (1 << 0)
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#define VGEN3STBY (1 << 1)
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