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* Patch by Yusdi Santoso, 22 Oct 2004:

Browse Source 
- Add support for HIDDEN_DRAGON board
  - fix endianess problem in driver/rtl1839.c

* Patch by Allen Curtis, 21 Oct 2004:
  support multiple serial ports
This commit is contained in:
wdenk 2005-04-03 15:51:42 +00:00
parent b1bf6f2c9b
commit 756f586a73
18 changed files with 1675 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
CHANGELOG
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@ -2,6 +2,13 @@
Changes for U-Boot 1.1.3:
======================================================================
* Patch by Yusdi Santoso, 22 Oct 2004:
- Add support for HIDDEN_DRAGON board
- fix endianess problem in driver/rtl1839.c
* Patch by Allen Curtis, 21 Oct 2004:
support multiple serial ports
* Patch by Richard Klingler, 03 Apr 2005:
Add call to eth_halt() in net/net.c when called functions fail
after eth_init() has been called.

4
MAINTAINERS
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@ -302,6 +302,10 @@ Dan Malek <dan@embeddededge.com>
STxGP3 MPC85xx
Yusdi Santoso <yusdi_santoso@adaptec.com>
HIDDEN_DRAGON MPC8241/MPC8245
-------------------------------------------------------------------------
Unknown / orphaned boards:

7
MAKEALL
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@ -86,9 +86,10 @@ LIST_8220=" \
LIST_824x=" \
A3000 BMW CPC45 CU824 \
debris eXalion MOUSSE MUSENKI \
MVBLUE OXC PN62 Sandpoint8240 \
Sandpoint8245 SL8245 utx8245 sbc8240 \
debris eXalion HIDDEN_DRAGON MOUSSE \
MUSENKI MVBLUE OXC PN62 \
Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
sbc8240 \
"
#########################################################################

3
Makefile
View File

@ -900,6 +900,9 @@ debris_config: unconfig
eXalion_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x eXalion
HIDDEN_DRAGON_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
MOUSSE_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x mousse

40
board/hidden_dragon/Makefile Normal file
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@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

60
board/hidden_dragon/README Normal file
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@ -0,0 +1,60 @@
U-Boot for Hidden Dragon board
------------------------------
Hidden Dragon is a MPC824x-based board by Motorola. For the most
part it is similar to Sandpoint8245 board. So unless otherwise
mentioned, the codes in this directory are adapted from ../sandpoint
directory.
Apparently there are very few of this board out there. Even Motorola
website does not have any info on it.
RAM:
start = 0x0000 0000
size = 0x0200 0000 (32 MB)
Flash:
BANK ONE:
start = 0xFFE0 0000
size = 0x0020 0000 (2 MB)
flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
flash sectors = 16K, 2x8K, 32K, 31x64K
BANK TWO:
NONE
The processor interrupt vectors reside on the first 256 bytes
starting from address 0xFFF00000. The "reset vector" (first
instruction executed after reset) is located on 0xFFF0 0100.
U-Boot is configured to reside in flash starting at the address of
0xFFF00000. The environment space is located in flash separately from
U-Boot, at the second sector of the first flash bank, starting from
0xFFE04000 until 0xFFE06000 (8KB).
Network:
- RTL8139 chip on the base board (SUPPORTED)
- RTL8129 chip on the processor board (NOT SUPPORTED)
Serial:
- Two NS16550 compatible UART on the processor board (SUPPORTED)
- One NS16550 compatible UART on the base board (UNTESTED)
Misc:
VIA686A PCI SuperIO peripheral controller
- 2 USB ports (UNTESTED)
- 2 PS2 ports (UNTESTED)
- Parallel port (UNTESTED)
- IDE & floppy interface (UNTESTED)
S3 Savage4 video card (UNTESTED)
TODO:
-----
- Support for the VIA686A based peripherals
- The RTL8139 driver frequently gives rx error.
- Support for RTL8129 network controller. (Why is the support removed from
rtl8139.c driver?)
(C) Copyright 2004
Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com

30
board/hidden_dragon/config.mk Normal file
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@ -0,0 +1,30 @@
#
# (C) Copyright 2000-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Hidden Dragon boards
#
TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

152
board/hidden_dragon/early_init.S Normal file
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@ -0,0 +1,152 @@
/*
* (C) Copyright 2001
* Thomas Koeller, tkoeller@gmx.net
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__ 1
#endif
#include <config.h>
#include <asm/processor.h>
#include <mpc824x.h>
#include <ppc_asm.tmpl>
#if defined(USE_DINK32)
/* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
#define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
#else
#define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
#endif
.text
/* Values to program into memory controller registers */
tbl: .long MCCR1, MCCR1VAL
.long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
.long MCCR3
.long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
(CFG_RDLAT << MCCR3_RDLAT_SHIFT)
.long MCCR4
.long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
(CFG_REGISTERD_TYPE_BUFFER << 20) | \
(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
.long MSAR1
.long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
.long EMSAR1
.long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
.long MSAR2
.long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
.long EMSAR2
.long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
.long MEAR1
.long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
.long EMEAR1
.long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
.long MEAR2
.long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
.long EMEAR2
.long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
.long 0
/*
* Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
* must be done in assembly, since we have no stack at this point.
*/
.global early_init_f
early_init_f:
mflr r10
/* basic memory controller configuration */
lis r3, CONFIG_ADDR_HIGH
lis r4, CONFIG_DATA_HIGH
bl lab
lab: mflr r5
lwzu r0, tbl - lab(r5)
loop: lwz r1, 4(r5)
stwbrx r0, 0, r3
eieio
stwbrx r1, 0, r4
eieio
lwzu r0, 8(r5)
cmpli cr0, 0, r0, 0
bne cr0, loop
/* set bank enable bits */
lis r0, MBER@h
ori r0, 0, MBER@l
li r1, CFG_BANK_ENABLE
stwbrx r0, 0, r3
eieio
stb r1, 0(r4)
eieio
/* delay loop */
lis r0, 0x0003
mtctr r0
delay: bdnz delay
/* enable memory controller */
lis r0, MCCR1@h
ori r0, 0, MCCR1@l
stwbrx r0, 0, r3
eieio
lwbrx r0, 0, r4
oris r0, 0, MCCR1_MEMGO@h
stwbrx r0, 0, r4
eieio
/* set up stack pointer */
lis r1, CFG_INIT_SP_OFFSET@h
ori r1, r1, CFG_INIT_SP_OFFSET@l
mtlr r10
blr

575
board/hidden_dragon/flash.c Normal file
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@ -0,0 +1,575 @@
/*
* (C) Copyright 2004
* Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc824x.h>
#include <asm/processor.h>
#include <asm/pci_io.h>
#include <w83c553f.h>
#define ROM_CS0_START 0xFF800000
#define ROM_CS1_START 0xFF000000
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# ifndef CFG_ENV_SECT_SIZE
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
# endif
#endif
/*-----------------------------------------------------------------------
* Functions
*/
static int write_word (flash_info_t *info, ulong dest, ulong data);
/*flash command address offsets*/
#define ADDR0 (0xAAA)
#define ADDR1 (0x555)
#define ADDR3 (0x001)
#define FLASH_WORD_SIZE unsigned char
/*-----------------------------------------------------------------------
*/
static unsigned long flash_id (unsigned char mfct, unsigned char chip)
__attribute__ ((const));
typedef struct {
FLASH_WORD_SIZE extval;
unsigned short intval;
} map_entry;
static unsigned long flash_id (unsigned char mfct, unsigned char chip)
{
static const map_entry mfct_map[] = {
{(FLASH_WORD_SIZE) AMD_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
{(FLASH_WORD_SIZE) FUJ_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
{(FLASH_WORD_SIZE) STM_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
{(FLASH_WORD_SIZE) MT_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
{(FLASH_WORD_SIZE) INTEL_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
};
static const map_entry chip_map[] = {
{AMD_ID_F040B, FLASH_AM040},
{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
};
const map_entry *p;
unsigned long result = FLASH_UNKNOWN;
/* find chip id */
for (p = &chip_map[0];
p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
if (p->extval == chip) {
result = FLASH_VENDMASK | p->intval;
break;
}
/* find vendor id */
for (p = &mfct_map[0];
p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
if (p->extval == mfct) {
result &= ~FLASH_VENDMASK;
result |= (unsigned long) p->intval << 16;
break;
}
return result;
}
unsigned long flash_init (void)
{
unsigned long i;
unsigned char j;
static const ulong flash_banks[] = CFG_FLASH_BANKS;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
flash_info_t *const pflinfo = &flash_info[i];
pflinfo->flash_id = FLASH_UNKNOWN;
pflinfo->size = 0;
pflinfo->sector_count = 0;
}
/* Enable writes to Hidden Dragon flash */
{
register unsigned char temp;
CONFIG_READ_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
temp);
temp &= ~0x20; /* clear BIOSWP bit */
CONFIG_WRITE_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
temp);
}
for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
flash_info_t *const pflinfo = &flash_info[i];
const unsigned long base_address = flash_banks[i];
volatile FLASH_WORD_SIZE *const flash =
(FLASH_WORD_SIZE *) base_address;
flash[0xAAA << (3 * i)] = 0xaa;
flash[0x555 << (3 * i)] = 0x55;
flash[0xAAA << (3 * i)] = 0x90;
__asm__ __volatile__ ("sync");
pflinfo->flash_id =
flash_id (flash[0x0], flash[0x2 + 14 * i]);
switch (pflinfo->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
pflinfo->size = 0x00080000;
pflinfo->sector_count = 8;
for (j = 0; j < 8; j++) {
pflinfo->start[j] =
base_address + 0x00010000 * j;
pflinfo->protect[j] = flash[(j << 16) | 0x2];
}
break;
case FLASH_STM800AB:
pflinfo->size = 0x00100000;
pflinfo->sector_count = 19;
pflinfo->start[0] = base_address;
pflinfo->start[1] = base_address + 0x4000;
pflinfo->start[2] = base_address + 0x6000;
pflinfo->start[3] = base_address + 0x8000;
for (j = 1; j < 16; j++) {
pflinfo->start[j + 3] =
base_address + 0x00010000 * j;
}
break;
default:
/* The chip used is not listed in flash_id
TODO: Change this to explicitly detect the flash type
*/
{
int sector_addr = base_address;
pflinfo->size = 0x00200000;
pflinfo->sector_count = 35;
pflinfo->start[0] = sector_addr;
sector_addr += 0x4000; /* 16K */
pflinfo->start[1] = sector_addr;
sector_addr += 0x2000; /* 8K */
pflinfo->start[2] = sector_addr;
sector_addr += 0x2000; /* 8K */
pflinfo->start[3] = sector_addr;
sector_addr += 0x8000; /* 32K */
for (j = 4; j < 35; j++) {
pflinfo->start[j] = sector_addr;
sector_addr += 0x10000; /* 64K */
}
}
break;
}
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
#endif
/* reset device to read mode */
flash[0x0000] = 0xf0;
__asm__ __volatile__ ("sync");
}
/* only have 1 bank */
return flash_info[0].size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
static const char unk[] = "Unknown";
const char *mfct = unk, *type = unk;
unsigned int i;
if (info->flash_id != FLASH_UNKNOWN) {
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
mfct = "AMD";
break;
case FLASH_MAN_FUJ:
mfct = "FUJITSU";
break;
case FLASH_MAN_STM:
mfct = "STM";
break;
case FLASH_MAN_SST:
mfct = "SST";
break;
case FLASH_MAN_BM:
mfct = "Bright Microelectonics";
break;
case FLASH_MAN_INTEL:
mfct = "Intel";
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
type = "AM29F040B (512K * 8, uniform sector size)";
break;
case FLASH_AM400B:
type = "AM29LV400B (4 Mbit, bottom boot sect)";
break;
case FLASH_AM400T:
type = "AM29LV400T (4 Mbit, top boot sector)";
break;
case FLASH_AM800B:
type = "AM29LV800B (8 Mbit, bottom boot sect)";
break;
case FLASH_AM800T:
type = "AM29LV800T (8 Mbit, top boot sector)";
break;
case FLASH_AM160T:
type = "AM29LV160T (16 Mbit, top boot sector)";
break;
case FLASH_AM320B:
type = "AM29LV320B (32 Mbit, bottom boot sect)";
break;
case FLASH_AM320T:
type = "AM29LV320T (32 Mbit, top boot sector)";
break;
case FLASH_STM800AB:
type = "M29W800AB (8 Mbit, bottom boot sect)";
break;
case FLASH_SST800A:
type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
break;
case FLASH_SST160A:
type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
break;
}
}
printf ("\n Brand: %s Type: %s\n"
" Size: %lu KB in %d Sectors\n",
mfct, type, info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
unsigned long size;
unsigned int erased;
unsigned long *flash = (unsigned long *) info->start[i];
/*
* Check if whole sector is erased
*/
size = (i != (info->sector_count - 1)) ?
(info->start[i + 1] - info->start[i]) >> 2 :
(info->start[0] + info->size - info->start[i]) >> 2;
for (flash = (unsigned long *) info->start[i], erased = 1;
(flash != (unsigned long *) info->start[i] + size)
&& erased; flash++)
erased = *flash == ~0x0UL;
printf ("%s %08lX %s %s",
(i % 5) ? "" : "\n ",
info->start[i],
erased ? "E" : " ", info->protect[i] ? "RO" : " ");
}
puts ("\n");
return;
}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
unsigned char sh8b;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Check the ROM CS */
if ((info->start[0] >= ROM_CS1_START)
&& (info->start[0] < ROM_CS0_START))
sh8b = 3;
else
sh8b = 0;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (FLASH_WORD_SIZE *) (info->start[0] +
((info->start[sect] -
info->start[0]) << sh8b));
if (info->flash_id & FLASH_MAN_SST) {
addr[ADDR0 << sh8b] =
(FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1 << sh8b] =
(FLASH_WORD_SIZE) 0x00550055;
addr[ADDR0 << sh8b] =
(FLASH_WORD_SIZE) 0x00800080;
addr[ADDR0 << sh8b] =
(FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1 << sh8b] =
(FLASH_WORD_SIZE) 0x00550055;
addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
udelay (30000); /* wait 30 ms */
} else
addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
info->
start[0]) << sh8b));
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
(FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
serial_putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (FLASH_WORD_SIZE *) info->start[0];
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_word (info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
volatile FLASH_WORD_SIZE *dest2;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int flag;
int i;
unsigned char sh8b;
/* Check the ROM CS */
if ((info->start[0] >= ROM_CS1_START)
&& (info->start[0] < ROM_CS0_START))
sh8b = 3;
else
sh8b = 0;
dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
info->start[0]);
/* Check if Flash is (sufficiently) erased */
if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
dest2[i << sh8b] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}

95
board/hidden_dragon/hidden_dragon.c Normal file
View File

@ -0,0 +1,95 @@
/*
* (C) Copyright 2004
* Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
int checkboard (void)
{
/*TODO: Check processor type */
puts ( "Board: Hidden Dragon "
#ifdef CONFIG_MPC8240
"8240"
#endif
#ifdef CONFIG_MPC8245
"8245"
#endif
" ##Test not implemented yet##\n");
/* TODO: Implement board test */
return 0;
}
long int initdram (int board_type)
{
long size;
long new_bank0_end;
long mear1;
long emear1;
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
return (size);
}
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_hidden_dragon_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
PCI_ENET1_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ }
};
#endif
struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_hidden_dragon_config_table,
#endif
};
void pci_init_board(void)
{
pci_mpc824x_init(&hose);
}

54
board/hidden_dragon/speed.h Normal file
View File

@ -0,0 +1,54 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*-----------------------------------------------------------------------
* Timer value for timer 2, ICLK = 10
*
* SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
* SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
*
* SPEED_FCOUNT2 timer 2 counting frequency
* GCLK CPU clock
* SPEED_TMR2_PS prescaler
*/
#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
/*-----------------------------------------------------------------------
* Timer value for PIT
*
* PIT_TIME = SPEED_PITC / PITRTCLK
* PITRTCLK = 8192
*/
#define SPEED_PITC (82 << 16) /* start counting from 82 */
/*
* The new value for PTA is calculated from
*
* PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
*
* gclk CPU clock (not bus clock !)
* Trefresh Refresh cycle * 4 (four word bursts used)
* DFBRG For normal mode (no clock reduction) always 0
* PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
* NCS Number of SDRAM banks (chip selects) on this UPM.
*/

130
board/hidden_dragon/u-boot.lds Normal file
View File

@ -0,0 +1,130 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc824x/start.o (.text)
lib_ppc/board.o (.text)
lib_ppc/ppcstring.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
drivers/rtl8139.c
View File

@ -254,7 +254,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
for (i = 0; i < 3; i++)
*ap++ = read_eeprom(i + 7, addr_len);
*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;

144
drivers/serial.c
View File

@ -30,28 +30,61 @@
#include <ns87308.h>
#endif
#if CONFIG_CONS_INDEX == 1
static NS16550_t console = (NS16550_t) CFG_NS16550_COM1;
#elif CONFIG_CONS_INDEX == 2
static NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
#elif CONFIG_CONS_INDEX == 3
static NS16550_t console = (NS16550_t) CFG_NS16550_COM3;
#elif CONFIG_CONS_INDEX == 4
static NS16550_t console = (NS16550_t) CFG_NS16550_COM4;
#else
#error no valid console defined
#if !defined(CONFIG_CONS_INDEX)
#error "No console index specified."
#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
#error "Invalid console index value."
#endif
static int calc_divisor (void)
#if CONFIG_CONS_INDEX == 1 && !defined(CFG_NS16550_COM1)
#error "Console port 1 defined but not configured."
#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_NS16550_COM2)
#error "Console port 2 defined but not configured."
#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_NS16550_COM3)
#error "Console port 3 defined but not configured."
#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_NS16550_COM4)
#error "Console port 4 defined but not configured."
#endif
/* Note: The port number specified in the functions is 1 based.
* the array is 0 based.
*/
static NS16550_t serial_ports[4] = {
#ifdef CFG_NS16550_COM1
(NS16550_t)CFG_NS16550_COM1,
#else
NULL,
#endif
#ifdef CFG_NS16550_COM2
(NS16550_t)CFG_NS16550_COM2,
#else
NULL,
#endif
#ifdef CFG_NS16550_COM3
(NS16550_t)CFG_NS16550_COM3,
#else
NULL,
#endif
#ifdef CFG_NS16550_COM4
(NS16550_t)CFG_NS16550_COM4
#else
NULL
#endif
};
#define PORT serial_ports[port-1]
#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1])
static int calc_divisor (NS16550_t port)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_OMAP1510
/* If can't cleanly clock 115200 set div to 1 */
if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
console->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
return (1); /* return 1 for base divisor */
}
console->osc_12m_sel = 0; /* clear if previsouly set */
port->osc_12m_sel = 0; /* clear if previsouly set */
#endif
#ifdef CONFIG_OMAP1610
/* If can't cleanly clock 115200 set div to 1 */
@ -71,54 +104,111 @@ static int calc_divisor (void)
int serial_init (void)
{
int clock_divisor = calc_divisor();
int clock_divisor;
#ifdef CFG_NS87308
initialise_ns87308();
#endif
NS16550_init(console, clock_divisor);
#ifdef CFG_NS16550_COM1
clock_divisor = calc_divisor(serial_ports[0]);
NS16550_init(serial_ports[0], clock_divisor);
#endif
#ifdef CFG_NS16550_COM2
clock_divisor = calc_divisor(serial_ports[1]);
NS16550_init(serial_ports[1], clock_divisor);
#endif
#ifdef CFG_NS16550_COM3
clock_divisor = calc_divisor(serial_ports[2]);
NS16550_init(serial_ports[2], clock_divisor);
#endif
#ifdef CFG_NS16550_COM4
clock_divisor = calc_divisor(serial_ports[3]);
NS16550_init(serial_ports[3], clock_divisor);
#endif
return (0);
}
void
serial_putc(const char c)
_serial_putc(const char c,const int port)
{
if (c == '\n')
NS16550_putc(console, '\r');
NS16550_putc(PORT, '\r');
NS16550_putc(console, c);
NS16550_putc(PORT, c);
}
void
serial_puts (const char *s)
_serial_putc_raw(const char c,const int port)
{
NS16550_putc(PORT, c);
}
void
_serial_puts (const char *s,const int port)
{
while (*s) {
serial_putc (*s++);
_serial_putc (*s++,port);
}
}
int
_serial_getc(const int port)
{
return NS16550_getc(PORT);
}
int
_serial_tstc(const int port)
{
return NS16550_tstc(PORT);
}
void
_serial_setbrg (const int port)
{
int clock_divisor;
clock_divisor = calc_divisor(PORT);
NS16550_reinit(PORT, clock_divisor);
}
void
serial_putc(const char c)
{
_serial_putc(c,CONFIG_CONS_INDEX);
}
void
serial_putc_raw(const char c)
{
_serial_putc_raw(c,CONFIG_CONS_INDEX);
}
void
serial_puts(const char *s)
{
_serial_puts(s,CONFIG_CONS_INDEX);
}
int
serial_getc(void)
{
return NS16550_getc(console);
return _serial_getc(CONFIG_CONS_INDEX);
}
int
serial_tstc(void)
{
return NS16550_tstc(console);
return _serial_tstc(CONFIG_CONS_INDEX);
}
void
serial_setbrg (void)
serial_setbrg(void)
{
int clock_divisor;
clock_divisor = calc_divisor();
NS16550_reinit(console, clock_divisor);
_serial_setbrg(CONFIG_CONS_INDEX);
}
#endif

5
include/asm-ppc/global_data.h
View File

@ -71,9 +71,10 @@ typedef struct global_data {
#if defined(CFG_GT_6426x)
unsigned int mirror_hack[16];
#endif
#if defined(CONFIG_SANDPOINT) || \
#if defined(CONFIG_A3000) || \
defined(CONFIG_HIDDEN_DRAGON) || \
defined(CONFIG_MUSENKI) || \
defined(CONFIG_A3000)
defined(CONFIG_SANDPOINT)
void * console_addr;
#endif
#ifdef CONFIG_AMIGAONEG3SE

3
include/asm-ppc/processor.h
View File

@ -818,6 +818,7 @@
#define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */
#define _MACH_tqm860 0x00008000 /* TQM860/L */
#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */
#define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */
/* see residual.h for these */
@ -1036,6 +1037,8 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
#define have_of 0
#elif defined(CONFIG_SANDPOINT)
#define _machine _MACH_sandpoint
#elif defined(CONFIG_HIDDEN_DRAGON)
#define _machine _MACH_hidden_dragon
#define have_of 0
#else
#error "Machine not defined correctly"

10
include/common.h
View File

@ -386,13 +386,21 @@ ulong get_tbclk (void);
/* $(CPU)/serial.c */
int serial_init (void);
void serial_addr (unsigned int);
void serial_setbrg (void);
void serial_putc (const char);
void serial_putc_raw(const char);
void serial_puts (const char *);
void serial_addr (unsigned int);
int serial_getc (void);
int serial_tstc (void);
void _serial_setbrg (const int);
void _serial_putc (const char, const int);
void _serial_putc_raw(const char, const int);
void _serial_puts (const char *, const int);
int _serial_getc (const int);
int _serial_tstc (const int);
/* $(CPU)/speed.c */
int get_clocks (void);
int get_clocks_866 (void);

387
include/configs/HIDDEN_DRAGON.h Normal file
View File

@ -0,0 +1,387 @@
/*
* (C) Copyright 2004
* Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
*
* (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* ------------------------------------------------------------------------- */
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_HIDDEN_DRAGON 1
#if 0
#define USE_DINK32 1
#else
#undef USE_DINK32
#endif
#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
#define CONFIG_BAUDRATE 9600
#define CONFIG_DRAM_SPEED 100 /* MHz */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_NET | \
CFG_CMD_PCI | \
CFG_CMD_PING )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP 1 /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define PCI_ENET0_IOADDR 0x80000000
#define PCI_ENET0_MEMADDR 0x80000000
#define PCI_ENET1_IOADDR 0x81000000
#define PCI_ENET1_MEMADDR 0x81000000
#define CONFIG_RTL8139
#define _IO_BASE 0x00000000
/* This macro is used by RTL8139 but not defined in PPC architecture */
#define KSEG1ADDR(x) (x)
/* Make sure the ethaddr can be overwritten
TODO: Remove this on final product
*/
#define CONFIG_ENV_OVERWRITE
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_MAX_RAM_SIZE 0x02000000
#define CFG_RESET_ADDRESS 0xFFF00100
#if defined (USE_DINK32)
#define CFG_MONITOR_LEN 0x00030000
#define CFG_MONITOR_BASE 0x00090000
#define CFG_RAMBOOT 1
#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_INIT_RAM_END 0x10000
#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#else
#undef CFG_RAMBOOT
#define CFG_MONITOR_LEN 0x00030000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_GBL_DATA_SIZE 128
#define CFG_INIT_RAM_ADDR 0x40000000
#define CFG_INIT_RAM_END 0x1000
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#endif
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
#define CFG_EUMB_ADDR 0xFC000000
#define CFG_ISA_MEM 0xFD000000
#define CFG_ISA_IO 0xFE000000
#define CFG_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */
#define CFG_FLASH_RANGE_SIZE 0x00200000
#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */
/*
* select i2c support configuration
*
* Supported configurations are {none, software, hardware} drivers.
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#ifdef CONFIG_SOFT_I2C
#error "Soft I2C is not configured properly. Please review!"
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
else iop->pdat &= ~0x00010000
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM }
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
/* TODO: Change this to VIA686A */
/*
* NS87308 Configuration
*/
#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
#define CFG_NS87308_BADDR_10 1
#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
CFG_NS87308_UART2 | \
CFG_NS87308_POWRMAN | \
CFG_NS87308_RTC_APC )
#undef CFG_NS87308_PS2MOD
#define CFG_NS87308_CS0_BASE 0x0076
#define CFG_NS87308_CS0_CONF 0x30
#define CFG_NS87308_CS1_BASE 0x0075
#define CFG_NS87308_CS1_CONF 0x30
#define CFG_NS87308_CS2_BASE 0x0074
#define CFG_NS87308_CS2_CONF 0x30
/*
* NS16550 Configuration
*/
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#if (CONFIG_CONS_INDEX > 2)
#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000
#else
#define CFG_NS16550_CLK 1843200
#endif
#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600)
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CFG_ROMNAL 7 /*rom/flash next access time */
#define CFG_ROMFAL 11 /*rom/flash access time */
#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
/* the following are for SDRAM only*/
#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
#define CFG_REFREC 8 /* Refresh to activate interval */
#define CFG_RDLAT 4 /* data latency from read command */
#define CFG_PRETOACT 3 /* Precharge to activate interval */
#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
#define CFG_ACTORW 3 /* Activate to R/W */
#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
#if 0
#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
#endif
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM 1
#define CFG_REGDIMM 0
/* memory bank settings*/
/*
* only bits 20-29 are actually used from these vales to set the
* start/end address the upper two bits will be 0, and the lower 20
* bits will be set to 0x00000 for a start address, or 0xfffff for an
* end address
*/
#define CFG_BANK0_START 0x00000000
#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE 1
#define CFG_BANK1_START 0x3ff00000
#define CFG_BANK1_END 0x3fffffff
#define CFG_BANK1_ENABLE 0
#define CFG_BANK2_START 0x3ff00000
#define CFG_BANK2_END 0x3fffffff
#define CFG_BANK2_ENABLE 0
#define CFG_BANK3_START 0x3ff00000
#define CFG_BANK3_END 0x3fffffff
#define CFG_BANK3_ENABLE 0
#define CFG_BANK4_START 0x00000000
#define CFG_BANK4_END 0x00000000
#define CFG_BANK4_ENABLE 0
#define CFG_BANK5_START 0x00000000
#define CFG_BANK5_END 0x00000000
#define CFG_BANK5_ENABLE 0
#define CFG_BANK6_START 0x00000000
#define CFG_BANK6_END 0x00000000
#define CFG_BANK6_ENABLE 0
#define CFG_BANK7_START 0x00000000
#define CFG_BANK7_END 0x00000000
#define CFG_BANK7_ENABLE 0
/*
* Memory bank enable bitmask, specifying which of the banks defined above
are actually present. MSB is for bank #7, LSB is for bank #0.
*/
#define CFG_BANK_ENABLE 0x01
#define CFG_ODCR 0xff /* configures line driver impedances, */
/* see 8240 book for bit definitions */
#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
/* currently accessed page in memory */
/* see 8240 book for details */
/* SDRAM 0 - 256MB */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
/* stack in DCACHE @ 1GB (no backing mem) */
#if defined(USE_DINK32)
#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
#else
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#endif
/* PCI memory */
#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/* Flash, config addrs, etc */
#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 36 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ
#undef NR_8259_INTS
#define NR_8259_INTS 1
#define CONFIG_DISK_SPINUP_TIME 1000000
#endif /* __CONFIG_H */