Merge branch 'xnext/zynqmp' of git://www.denx.de/git/u-boot-microblaze

MAINTAINERS

@@ -172,6 +172,12 @@ S:	Maintained
 F:	arch/arm/cpu/armv7/zynq/
 F:	arch/arm/include/asm/arch-zynq/
 
+ARM ZYNQMP
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+F:	arch/arm/cpu/armv8/zynqmp/
+F:	arch/arm/include/asm/arch-zynqmp/
+
 AVR32
 M:	Andreas Bießmann <andreas.devel@googlemail.com>
 S:	Maintained

arch/arm/Kconfig

@@ -592,6 +592,10 @@ config ZYNQ
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_XILINX_ZYNQMP
+	bool "Support Xilinx ZynqMP Platform"
+	select ARM64
+
 config TEGRA
 	bool "NVIDIA Tegra"
 	select SUPPORT_SPL
@@ -840,6 +844,7 @@ source "board/vpac270/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/xaeniax/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
 source "board/zipitz2/Kconfig"
 
 source "arch/arm/Kconfig.debug"

arch/arm/cpu/armv8/Makefile

@@ -16,3 +16,4 @@ obj-y	+= tlb.o
 obj-y	+= transition.o
 
 obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
+obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/

arch/arm/cpu/armv8/zynqmp/Makefile

@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014 - 2015 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= clk.o
+obj-y	+= cpu.o

arch/arm/cpu/armv8/zynqmp/clk.c

@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long get_uart_clk(int dev_id)
+{
+	u32 ver = zynqmp_get_silicon_version();
+
+	switch (ver) {
+	case ZYNQMP_CSU_VERSION_EP108:
+		return 25000000;
+	}
+
+	return 133000000;
+}
+
+#ifdef CONFIG_CLOCKS
+/**
+ * set_cpu_clk_info() - Initialize clock framework
+ * Always returns zero.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+	gd->cpu_clk = get_tbclk();
+
+	/* Support Veloce to show at least 1MHz via bdi */
+	if (gd->cpu_clk > 1000000)
+		gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+	else
+		gd->bd->bi_arm_freq = 1;
+
+	gd->bd->bi_dsp_freq = 0;
+
+	return 0;
+}
+#endif

arch/arm/cpu/armv8/zynqmp/cpu.c

@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+#define ZYNQ_SILICON_VER_MASK	0xF000
+#define ZYNQ_SILICON_VER_SHIFT	12
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int zynqmp_get_silicon_version(void)
+{
+	gd->cpu_clk = get_tbclk();
+
+	switch (gd->cpu_clk) {
+	case 50000000:
+		return ZYNQMP_CSU_VERSION_QEMU;
+	}
+
+	return ZYNQMP_CSU_VERSION_EP108;
+}

arch/arm/include/asm/arch-zynqmp/clk.h

@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CLK_H_
+#define _ASM_ARCH_CLK_H_
+
+unsigned long get_uart_clk(int dev_id);
+
+#endif /* _ASM_ARCH_CLK_H_ */

arch/arm/include/asm/arch-zynqmp/hardware.h

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define ZYNQ_SERIAL_BASEADDR0	0xFF000000
+#define ZYNQ_SERIAL_BASEADDR1	0xFF001000
+
+#define ZYNQ_SDHCI_BASEADDR0	0xFF160000
+#define ZYNQ_SDHCI_BASEADDR1	0xFF170000
+
+#define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
+#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
+
+struct crlapb_regs {
+	u32 reserved0[74];
+	u32 timestamp_ref_ctrl; /* 0x128 */
+	u32 reserved0_1[53];
+	u32 boot_mode; /* 0x200 */
+	u32 reserved1[26];
+};
+
+#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
+
+#define ZYNQMP_IOU_SCNTR	0xFF250000
+#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN	0x1
+#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG	0x2
+
+struct iou_scntr {
+	u32 counter_control_register;
+	u32 reserved0[7];
+	u32 base_frequency_id_register;
+};
+
+#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
+
+/* Bootmode setting values */
+#define BOOT_MODES_MASK	0x0000000F
+#define SD_MODE		0x00000005
+#define JTAG_MODE	0x00000000
+
+/* Board version value */
+#define ZYNQMP_CSU_VERSION_SILICON	0x0
+#define ZYNQMP_CSU_VERSION_EP108	0x1
+#define ZYNQMP_CSU_VERSION_QEMU		0x3
+
+#endif /* _ASM_ARCH_HARDWARE_H */

arch/arm/include/asm/arch-zynqmp/sys_proto.h

@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+int zynq_sdhci_init(unsigned long regbase);
+
+unsigned int zynqmp_get_silicon_version(void);
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */

board/xilinx/zynqmp/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_XILINX_ZYNQMP
+
+config SYS_BOARD
+	default "zynqmp"
+
+config SYS_VENDOR
+	default "xilinx"
+
+config SYS_SOC
+	default "zynqmp"
+
+config SYS_CONFIG_NAME
+	default "xilinx_zynqmp"
+
+endif

board/xilinx/zynqmp/MAINTAINERS

@@ -0,0 +1,6 @@
+XILINX_ZYNQMP BOARD
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+F:	board/xilinx/zynqmp/
+F:	include/configs/xilinx_zynqmp.h
+F:	configs/xilinx_zynqmp_defconfig

board/xilinx/zynqmp/Makefile

@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 - 2015 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= zynqmp.o

board/xilinx/zynqmp/zynqmp.c

@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	u32 val;
+
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+	writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+	/* Program freq register in System counter and enable system counter */
+	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
+	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
+	       ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+	       &iou_scntr->counter_control_register);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int timer_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bd)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ZYNQ_SDHCI)
+# if defined(CONFIG_ZYNQ_SDHCI0)
+	ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
+# endif
+# if defined(CONFIG_ZYNQ_SDHCI1)
+	ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
+# endif
+#endif
+
+	return ret;
+}
+#endif
+
+int board_late_init(void)
+{
+	u32 reg = 0;
+	u8 bootmode;
+
+	reg = readl(&crlapb_base->boot_mode);
+	bootmode = reg & BOOT_MODES_MASK;
+
+	switch (bootmode) {
+	case SD_MODE:
+		setenv("modeboot", "sdboot");
+		break;
+	default:
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	return 0;
+}

configs/xilinx_zynqmp_defconfig

@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_TARGET_XILINX_ZYNQMP=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_TIMER=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp"

include/configs/xilinx_zynqmp.h

@@ -0,0 +1,131 @@
+/*
+ * Configuration for Xilinx ZynqMP
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * Based on Configuration for Versatile Express
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __XILINX_ZYNQMP_H
+#define __XILINX_ZYNQMP_H
+
+#define CONFIG_REMAKE_ELF
+
+/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE	0xF9010000
+#define GICC_BASE	0xF9020000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_SDRAM_SIZE
+
+/* Have release address at the end of 256MB for now */
+#define CPU_RELEASE_ADDR	0xFFFFFF0
+
+/* Cache Definitions */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_IDENT_STRING		" Xilinx ZynqMP"
+
+#define CONFIG_SYS_TEXT_BASE		0x8000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
+#define COUNTER_FREQUENCY		4000000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x400000)
+
+/* Serial setup */
+#define CONFIG_ZYNQ_SERIAL_UART0
+#define CONFIG_ZYNQ_SERIAL
+
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{ 4800, 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MEMORY
+#define CONFIG_DOS_PARTITION
+
+#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+# define CONFIG_MMC
+# define CONFIG_GENERIC_MMC
+# define CONFIG_SDHCI
+# define CONFIG_ZYNQ_SDHCI
+# define CONFIG_CMD_MMC
+#endif
+
+#if defined(CONFIG_ZYNQ_SDHCI)
+# define CONFIG_FAT_WRITE
+# define CONFIG_CMD_EXT4_WRITE
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		0x8000000
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_addr=0x80000\0" \
+	"fdt_addr=0x7000000\0" \
+	"fdt_high=0x10000000\0" \
+	"sdboot=mmcinfo && fatload mmc 0:0 $fdt_addr system.dtb && " \
+		"fatload mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0"
+
+#define CONFIG_BOOTARGS		"setenv bootargs console=ttyPS0,${baudrate} " \
+				"earlycon=cdns,mmio,0xff000000,${baudrate}n8"
+#define CONFIG_PREBOOT		"run bootargs"
+#define CONFIG_BOOTCOMMAND	"run $modeboot"
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Do not preserve environment */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x1000
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_PROMPT		"ZynqMP> "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_MAXARGS		64
+
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE       /* enable fit_format_{error,warning}() */
+
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
+
+#define CONFIG_CMD_BOOTI
+#define CONFIG_CMD_UNZIP
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_CLOCKS
+
+#endif /* __XILINX_ZYNQMP_H */