sh: Add support ESPT-GIGA borad
ESPT-Giga is SH7763-based reference board. Board support is relatively sparse, presently supporting serial, gigabit ethernet, USB host, and MTD. More information (in Japanese) available at: http://www.cente.jp/product/cente_hard/ESPT-Giga.html Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
Nobuhiro Iwamatsu
parent
baa9f9ba43
commit
74d9c16a68
1
MAKEALL
1
MAKEALL
@ -848,6 +848,7 @@ LIST_sh4=" \
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sh7763rdp \
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sh7785lcr \
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ap325rxa \
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espt \
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"
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LIST_sh=" \
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5
Makefile
5
Makefile
@ -3545,6 +3545,11 @@ ap325rxa_config : unconfig
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@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
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@$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa renesas
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espt_config : unconfig
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@mkdir -p $(obj)include
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@echo "#define CONFIG_ESPT 1" > $(obj)include/config.h
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@$(MKCONFIG) -a $(@:_config=) sh sh4 espt
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#========================================================================
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# SPARC
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#========================================================================
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50
board/espt/Makefile
Normal file
50
board/espt/Makefile
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@ -0,0 +1,50 @@
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#
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# Copyright (C) 2009 Renesas Solutions Corp.
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# Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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#
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# board/espt/Makefile
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := espt.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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9
board/espt/config.mk
Normal file
9
board/espt/config.mk
Normal file
@ -0,0 +1,9 @@
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#
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# board/espt/config.mk
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#
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# TEXT_BASE refers to image _after_ relocation.
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#
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# NOTE: Must match value used in u-boot.lds (in this directory).
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#
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TEXT_BASE = 0x8FFC0000
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50
board/espt/espt.c
Normal file
50
board/espt/espt.c
Normal file
@ -0,0 +1,50 @@
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/*
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*
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* board/espt/espt.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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int checkboard(void)
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{
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puts("BOARD: ESPT-GIGA\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
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return 0;
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}
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void led_set_state(unsigned short value)
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{
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}
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334
board/espt/lowlevel_init.S
Normal file
334
board/espt/lowlevel_init.S
Normal file
@ -0,0 +1,334 @@
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/*
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*
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* board/espt/lowlevel_init.S
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 WDTCSR_A, WDTCSR_D
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write32 WDTST_A, WDTST_D
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write32 WDTBST_A, WDTBST_D
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write32 CCR_A, CCR_CACHE_ICI_D
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write32 MMUCR_A, MMU_CONTROL_TI_D
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write32 MSTPCR0_A, MSTPCR0_D
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write32 MSTPCR1_A, MSTPCR1_D
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write32 RAMCR_A, RAMCR_D
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/*
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* Setting infomation from
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* original ESPT-GIGA bootloader register
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*/
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write32 MMSEL_A, MMSEL_D
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/* dummy */
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mov.l @r1, r2
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mov.l @r1, r2
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synco
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write32 BCR_A, BCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS0WCR_A, CS0WCR_D
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/*
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* DDR-SDRAM setting
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*/
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/* set DDR-SDRAM dummy read */
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write32 MMSEL_A, MMSEL_D
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mov.l MMSEL_A, r0
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synco
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mov.l @r0, r1
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synco
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mov.l CS0_A, r0
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synco
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mov.l @r0, r1
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synco
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/* set DDR-SDRAM bus/endian etc */
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write32 MIM_U_A, MIM_U_D
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write32 MIM_L_A, MIM_L_D0
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write32 SDR_L_A, SDR_L_A_D0
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write32 STR_L_A, STR_L_A_D0
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/* DDR-SDRAM access control */
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write32 MIM_L_A, MIM_L_D1
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write32 SCR_L_A, SCR_L_A_D0
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write32 SCR_L_A, SCR_L_A_D1
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write32 EMRS_A, EMRS_D
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write32 MRS1_A, MRS1_D
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write32 MIM_U_A, MIM_U_D
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write32 MIM_L_A, MIM_L_A_D2
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write32 SCR_L_A, SCR_L_A_D2
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write32 SCR_L_A, SCR_L_A_D2
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write32 MRS2_A, MRS2_D
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/* wait 200us */
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wait_timer REPEAT_R3
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/* GPIO setting */
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write16 PSEL0_A, PSEL0_D
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write16 PSEL1_A, PSEL1_D
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write16 PSEL2_A, PSEL2_D
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write16 PSEL3_A, PSEL3_D
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write16 PSEL4_A, PSEL4_D
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write8 PADR_A, PADR_D
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write16 PACR_A, PACR_D
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write8 PBDR_A, PBDR_D
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write16 PBCR_A, PBCR_D
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write8 PCDR_A, PCDR_D
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write16 PCCR_A, PCCR_D
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write8 PDDR_A, PDDR_D
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write16 PDCR_A, PDCR_D
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write16 PECR_A, PECR_D
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write16 PFCR_A, PFCR_D
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write16 PGCR_A, PGCR_D
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write16 PHCR_A, PHCR_D
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write16 PICR_A, PICR_D
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write8 PJDR_A, PJDR_D
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write16 PJCR_A, PJCR_D
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/* wait 50us */
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wait_timer REPEAT_R3
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write8 PKDR_A, PKDR_D
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write16 PKCR_A, PKCR_D
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write16 PLCR_A, PLCR_D
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write16 PMCR_A, PMCR_D
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write16 PNCR_A, PNCR_D
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write16 POCR_A, POCR_D
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/* ICR0 ,ICR1 */
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write32 ICR0_A, ICR0_D
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write32 ICR1_A, ICR1_D
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/* USB Host */
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write32 USB_USBHSC_A, USB_USBHSC_D
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write32 CCR_A, CCR_CACHE_D_2
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rts
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nop
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.align 2
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/* GPIO Crontrol Register */
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PACR_A: .long 0xFFEF0000
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PBCR_A: .long 0xFFEF0002
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PCCR_A: .long 0xFFEF0004
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PDCR_A: .long 0xFFEF0006
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PECR_A: .long 0xFFEF0008
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PFCR_A: .long 0xFFEF000A
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PGCR_A: .long 0xFFEF000C
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PHCR_A: .long 0xFFEF000E
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PICR_A: .long 0xFFEF0010
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PJCR_A: .long 0xFFEF0012
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PKCR_A: .long 0xFFEF0014
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PLCR_A: .long 0xFFEF0016
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PMCR_A: .long 0xFFEF0018
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PNCR_A: .long 0xFFEF001A
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POCR_A: .long 0xFFEF001C
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/* GPIO Data Register */
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PADR_A: .long 0xFFEF0020
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PBDR_A: .long 0xFFEF0022
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PCDR_A: .long 0xFFEF0024
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PDDR_A: .long 0xFFEF0026
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PJDR_A: .long 0xFFEF0032
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PKDR_A: .long 0xFFEF0034
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/* GPIO Set data */
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PADR_D: .long 0x00000000
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PACR_D: .long 0x00001400
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PBDR_D: .long 0x00000000
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PBCR_D: .long 0x0000555A
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PCDR_D: .long 0x00000000
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PCCR_D: .long 0x00005555
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PDDR_D: .long 0x00000000
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PDCR_D: .long 0x00000155
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PECR_D: .long 0x00000000
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PFCR_D: .long 0x00000000
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PGCR_D: .long 0x00000000
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PHCR_D: .long 0x00000000
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PICR_D: .long 0x00000800
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PJDR_D: .long 0x00000006
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PJCR_D: .long 0x00005A57
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PKDR_D: .long 0x00000000
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PKCR_D: .long 0x0000FFF9
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PLCR_D: .long 0x0000C330
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PMCR_D: .long 0x0000FFFF
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PNCR_D: .long 0x00000242
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POCR_D: .long 0x00000000
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/* Pin Select */
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PSEL0_A: .long 0xFFEF0070
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PSEL1_A: .long 0xFFEF0072
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PSEL2_A: .long 0xFFEF0074
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PSEL3_A: .long 0xFFEF0076
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PSEL4_A: .long 0xFFEF0078
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PSEL0_D: .long 0x0001
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PSEL1_D: .long 0x2400
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PSEL2_D: .long 0x0000
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PSEL3_D: .long 0x2421
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PSEL4_D: .long 0x0000
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MMSEL_A: .long 0xFE600020
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BCR_A: .long 0xFF801000
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CS0BCR_A: .long 0xFF802000
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CS0WCR_A: .long 0xFF802008
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ICR0_A: .long 0xFFD00000
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ICR1_A: .long 0xFFD0001C
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MMSEL_D: .long 0xA5A50000
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BCR_D: .long 0x05000000
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CS0BCR_D: .long 0x232306F0
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CS0WCR_D: .long 0x00011104
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ICR0_D: .long 0x80C00000
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ICR1_D: .long 0x00020000
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/* RWBT Address */
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WDTST_A: .long 0xFFCC0000
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WDTCSR_A: .long 0xFFCC0004
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WDTBST_A: .long 0xFFCC0008
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/* RWBT Data */
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WDTST_D: .long 0x5A000FFF
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WDTCSR_D: .long 0xA5000000
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WDTBST_D: .long 0x55000000
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/* Cache Address */
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CCR_A: .long 0xFF00001C
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MMUCR_A: .long 0xFF000010
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RAMCR_A: .long 0xFF000074
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/* Cache Data */
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CCR_CACHE_ICI_D:.long 0x00000800
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CCR_CACHE_D_2: .long 0x00000103
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MMU_CONTROL_TI_D:.long 0x00000004
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RAMCR_D: .long 0x00000200
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/* Low power mode control Address */
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MSTPCR0_A: .long 0xFFC80030
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MSTPCR1_A: .long 0xFFC80038
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/* Low power mode control Data */
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MSTPCR0_D: .long 0x00000000
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MSTPCR1_D: .long 0x00000000
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REPEAT0_R3: .long 0x00002000
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REPEAT_R3: .long 0x00000200
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CS0_A: .long 0xA8000000
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MIM_U_A: .long 0xFE800008
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MIM_L_A: .long 0xFE80000C
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SCR_U_A: .long 0xFE800010
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SCR_L_A: .long 0xFE800014
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STR_U_A: .long 0xFE800018
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STR_L_A: .long 0xFE80001C
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SDR_U_A: .long 0xFE800030
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SDR_L_A: .long 0xFE800034
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EMRS_A: .long 0xFE902000
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MRS1_A: .long 0xFE900B08
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MRS2_A: .long 0xFE900308
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MIM_U_D: .long 0x00000000
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MIM_L_D0: .long 0x04100008
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MIM_L_D1: .long 0x02EE0009
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MIM_L_D2: .long 0x02EE0209
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SDR_L_A_D0: .long 0x00000300
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STR_L_A_D0: .long 0x00010040
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MIM_L_A_D1: .long 0x04100009
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SCR_L_A_D0: .long 0x00000003
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SCR_L_A_D1: .long 0x00000002
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MIM_L_A_D2: .long 0x04100209
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SCR_L_A_D2: .long 0x00000004
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SCR_L_NORMAL: .long 0x00000000
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SCR_L_NOP: .long 0x00000001
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SCR_L_PALL: .long 0x00000002
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SCR_L_CKE_EN: .long 0x00000003
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SCR_L_CBR: .long 0x00000004
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STR_L_D: .long 0x000F3980
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SDR_L_D: .long 0x00000400
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EMRS_D: .long 0x00000000
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MRS1_D: .long 0x00000000
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MRS2_D: .long 0x00000000
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/* USB */
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USB_USBHSC_A: .long 0xFFEC80F0
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USB_USBHSC_D: .long 0x00000000
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126
include/configs/espt.h
Normal file
126
include/configs/espt.h
Normal file
@ -0,0 +1,126 @@
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/*
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||||
* Configuation settings for the ESPT-GIGA board
|
||||
*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ESPT_H
|
||||
#define __ESPT_H
|
||||
|
||||
#define CONFIG_SH 1
|
||||
#define CONFIG_SH4 1
|
||||
#define CONFIG_CPU_SH7763 1
|
||||
#define CONFIG_ESPT 1
|
||||
#define __LITTLE_ENDIAN 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_CONSOLE 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_CONS_SCIF0 1
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
|
||||
#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
|
||||
#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments
|
||||
passed to kernel */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
|
||||
settings for this board */
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
|
||||
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
|
||||
|
||||
/* Flash(NOR) S29JL064H */
|
||||
#define CONFIG_SYS_FLASH_BASE (0xA0000000)
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS (1)
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (150)
|
||||
|
||||
/* U-boot setting */
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
|
||||
/* Size of DRAM reserved for malloc() use */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE (256)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#undef CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
/* Timeout for Flash erase operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash write operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash set sector lock bit operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
|
||||
/* Timeout for Flash clear lock bit operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
|
||||
/* Use hardware flash sectors protection instead of U-Boot software protection */
|
||||
#undef CONFIG_SYS_FLASH_PROTECTION
|
||||
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
|
||||
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
|
||||
|
||||
/* Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Ether */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_SH_ETHER 1
|
||||
#define CONFIG_SH_ETHER_USE_PORT (1)
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
|
||||
|
||||
#endif /* __SH7763RDP_H */
|
||||
Loading…
Reference in New Issue
Block a user