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spi: ti_qspi: Use 4-byte opcode for mmap read

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ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
memory-mapped read. This restricts maximum addressable flash size to
16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped
read to allow access to addresses above 16MB.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
[vigneshr@ti.com: Re-word commit description]
Signed-off-by: Vignesh R <vigneshr@ti.com>
This commit is contained in:
Vignesh R 2015-11-23 17:43:36 +05:30 committed by Tom Rini
parent 99e7fc8a26
commit 74d49bfde3
1 changed files with 3 additions and 3 deletions
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6
drivers/spi/ti_qspi.c
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@ -52,15 +52,15 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_CMD_READ (0x3 << 0) #define QSPI_CMD_READ (0x3 << 0)
#define QSPI_CMD_READ_DUAL (0x6b << 0) #define QSPI_CMD_READ_DUAL (0x6b << 0)
#define QSPI_CMD_READ_QUAD (0x6b << 0) #define QSPI_CMD_READ_QUAD (0x6c << 0)
#define QSPI_CMD_READ_FAST (0x0b << 0) #define QSPI_CMD_READ_FAST (0x0b << 0)
#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) #define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12) #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL (0x1 << 12) #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12) #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
#define QSPI_CMD_WRITE (0x2 << 16) #define QSPI_CMD_WRITE (0x12 << 16)
#define QSPI_NUM_DUMMY_BITS (0x0 << 24) #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
/* ti qspi register set */ /* ti qspi register set */