arm: kirkwood: Pogoplug-V4 : Add board implementation files
Add board header, defconfig, and implementation files for Pogoplug V4. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org>
This commit is contained in:
Tony Dinh
Stefan Roese
parent
71dcfa97fa
commit
7301ed9d68
6
board/cloudengines/pogo_v4/MAINTAINERS
Normal file
6
board/cloudengines/pogo_v4/MAINTAINERS
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@ -0,0 +1,6 @@
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POGO_V4 BOARD
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M: Tony Dinh <mibodhi@gmail.com>
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S: Maintained
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F: board/cloudengines/pogo_v4/
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F: include/configs/pogo_v4.h
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F: configs/pogo_v4_defconfig
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10
board/cloudengines/pogo_v4/Makefile
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10
board/cloudengines/pogo_v4/Makefile
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@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2014-2021 Tony Dinh <mibodhi@gmail.com>
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#
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# Based on
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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obj-y := pogo_v4.o
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148
board/cloudengines/pogo_v4/kwbimage.cfg
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148
board/cloudengines/pogo_v4/kwbimage.cfg
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@ -0,0 +1,148 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2012
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# David Purdy <david.c.purdy@gmail.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
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# Boot Media configurations (DONE)
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BOOT_FROM nand
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NAND_ECC_MODE default
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NAND_PAGE_SIZE 0x0800
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME)
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DATA 0xffd100e0 0x1b1b1b9b
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#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?)
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DATA 0xffd01400 0x43000618 # DDR Configuration register
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# bit13-0: 0x200 (200 DDR2 clks refresh rate)
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# bit23-14: zero
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# bit24: 1= enable exit self refresh mode on DDR access
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# bit25: 1 required
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# bit29-26: zero
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# bit31-30: 01
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DATA 0xffd01404 0x34143000 # DDR Controller Control Low
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# bit 4: 0=addr/cmd in smame cycle
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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# bit 6: 0=use recommended falling edge of clk for addr/cmd
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# bit14: 0=input buffer always powered up
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# bit18: 1=cpu lock transaction enabled
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# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 3 required
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# bit31: 0=no additional STARTBURST delay
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DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
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# bit3-0: TRAS lsbs
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# bit7-4: TRCD
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# bit11- 8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xffd0140c 0x00000819 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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# bit31-13: zero required
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DATA 0xffd01410 0x00000001 # DDR Address Control (changed to Dockstar vals)
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# bit1-0: 00, Cs0width=x16
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# bit3-2: 10, Cs0size=512Mb
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# bit5-4: 00, Cs2width=nonexistent
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# bit7-6: 00, Cs1size =nonexistent
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# bit9-8: 00, Cs2width=nonexistent
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# bit11-10: 00, Cs2size =nonexistent
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# bit13-12: 00, Cs3width=nonexistent
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# bit15-14: 00, Cs3size =nonexistent
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
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# bit31-20: 0 required
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DATA 0xffd01414 0x00000000 # DDR Open Pages Control
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# bit0: 0, OpenPage enabled
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# bit31-1: 0 required
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DATA 0xffd01418 0x00000000 # DDR Operation
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# bit3-0: 0x0, DDR cmd
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# bit31-4: 0 required
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DATA 0xffd0141c 0x00000632 # DDR Mode
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# bit2-0: 2, BurstLen=2 required
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# bit3: 0, BurstType=0 required
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# bit6-4: 4, CL=5 (<===== change to CL=3 ?)
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# bit7: 0, TestMode=0 normal
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# bit8: 0, DLL reset=0 normal
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# bit11-9: 6, auto-precharge write recovery ????????????
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# bit12: 0, PD must be zero
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# bit31-13: 0 required
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DATA 0xffd01420 0x00000040 # DDR Extended Mode
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# bit0: 0, DDR DLL enabled
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# bit1: 0, DDR drive strenght normal
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# bit2: 0, DDR ODT control lsd (disabled)
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# bit5-3: 000, required
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# bit6: 1, DDR ODT control msb, (disabled)
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# bit9-7: 000, required
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# bit10: 0, differential DQS enabled
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# bit11: 0, required
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# bit12: 0, DDR output buffer enabled
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# bit31-13: 0 required
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DATA 0xffd01424 0x0000F07F # DDR Controller Control High
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# bit2-0: 111, required
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# bit3 : 1 , MBUS Burst Chop disabled
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# bit6-4: 111, required
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# bit7 : 0
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# bit8 : 0 , no sample stage
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# bit9 : 0 , no half clock cycle addition to dataout
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
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# bit15-12: 1111 required
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# bit31-16: 0 required
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DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
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DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
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DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
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# bit0: 1, Window enabled
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# bit1: 0, Write Protect disabled
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# bit3-2: 00, CS0 hit selected
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# bit23-4: ones, required
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# bit31-24: 0x07, Size (i.e. 128MB)
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DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
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DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) (DONE)
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# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
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# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
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# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
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# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
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DATA 0xffd01498 0x00000000 # DDR ODT Control (High) (DONE)
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# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
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# bit3-2: 01, ODT1 active NEVER!
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# bit31-4: zero, required
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DATA 0xffd0149c 0x0000e803 # CPU ODT Control (DONE)
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DATA 0xffd01480 0x00000001 # DDR Initialization Control (DONE)
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#bit0=1, enable DDR init upon this register write
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# End of Header extension
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DATA 0x0 0x0
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148
board/cloudengines/pogo_v4/pogo_v4.c
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148
board/cloudengines/pogo_v4/pogo_v4.c
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@ -0,0 +1,148 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014-2022 Tony Dinh <mibodhi@gmail.com>
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*
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* Based on
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* Copyright (C) 2012 David Purdy <david.c.purdy@gmail.com>
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*
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* Based on Kirkwood support:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/mach-types.h>
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#include <bootstage.h>
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#include <command.h>
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#include <init.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO configuration */
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#define POGO_V4_OE_LOW (~(0))
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#define POGO_V4_OE_HIGH (~(0))
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#define POGO_V4_OE_VAL_LOW BIT(29)
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#define POGO_V4_OE_VAL_HIGH 0
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/* button */
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#define BTN_EJECT 29
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(POGO_V4_OE_VAL_LOW,
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POGO_V4_OE_VAL_HIGH,
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POGO_V4_OE_LOW, POGO_V4_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_SATA1_ACTn,
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MPP21_SATA0_ACTn,
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MPP22_GPIO, /* Green LED */
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MPP23_GPIO,
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MPP24_GPIO, /* Red LED */
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO, /* Eject button */
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO, /* FR6192 has only 36 GPIOs */
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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return cpu_eth_init(bis);
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}
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int board_late_init(void)
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{
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/* Do late init to ensure successful enumeration of XHCI devices */
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pci_init();
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return 0;
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}
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int board_init(void)
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{
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/* Boot parameters address */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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#if CONFIG_IS_ENABLED(BOOTSTAGE)
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#define GREEN_LED BIT(22)
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#define RED_LED BIT(24)
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#define BOTH_LEDS (GREEN_LED | RED_LED)
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#define NEITHER_LED 0
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static void set_leds(u32 leds, u32 blinking)
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{
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struct kwgpio_registers *r;
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u32 oe;
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u32 bl;
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r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
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oe = readl(&r->oe) | BOTH_LEDS;
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writel(oe & ~leds, &r->oe); /* active low */
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bl = readl(&r->blink_en) & ~BOTH_LEDS;
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writel(bl | blinking, &r->blink_en);
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}
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void show_boot_progress(int val)
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{
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switch (val) {
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case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
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set_leds(BOTH_LEDS, NEITHER_LED);
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break;
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case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
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set_leds(GREEN_LED, GREEN_LED);
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break;
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default:
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if (val < 0) /* error */
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set_leds(RED_LED, RED_LED);
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break;
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}
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}
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#endif
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79
configs/pogo_v4_defconfig
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79
configs/pogo_v4_defconfig
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CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_SYS_DCACHE_OFF=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_SYS_THUMB_BUILD=y
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CONFIG_ARCH_KIRKWOOD=y
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CONFIG_SYS_KWD_CONFIG="board/cloudengines/pogo_v4/kwbimage.cfg"
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CONFIG_SYS_TEXT_BASE=0x600000
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CONFIG_TARGET_POGO_V4=y
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_OFFSET=0xC0000
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CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogoplug-series-4"
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CONFIG_IDENT_STRING="\nPogoplug V4"
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CONFIG_SYS_LOAD_ADDR=0x800000
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CONFIG_BOOTSTAGE=y
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CONFIG_SHOW_BOOT_PROGRESS=y
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CONFIG_BOOTDELAY=10
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="setenv bootargs ${bootargs_console}; run bootcmd_usb; bootm 0x00800000 0x01100000 0x2c00000"
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CONFIG_USE_PREBOOT=y
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CONFIG_BOARD_LATE_INIT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="Pogo_V4> "
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CONFIG_CMD_BOOTZ=y
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# CONFIG_BOOTM_PLAN9 is not set
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# CONFIG_BOOTM_RTEMS is not set
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# CONFIG_BOOTM_VXWORKS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_NAND=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_SATA=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_SNTP=y
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CONFIG_CMD_DNS=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_JFFS2=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:2M(u-boot),3M(uImage),3M(uImage2),8M(failsafe),112M(root)"
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CONFIG_CMD_UBI=y
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CONFIG_ISO_PARTITION=y
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CONFIG_EFI_PARTITION=y
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CONFIG_PARTITION_TYPE_GUID=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_NAND=y
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CONFIG_VERSION_VARIABLE=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_NETCONSOLE=y
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CONFIG_DM=y
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CONFIG_SATA_MV=y
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CONFIG_KIRKWOOD_GPIO=y
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# CONFIG_MMC_HW_PARTITIONING is not set
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CONFIG_MVEBU_MMC=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_DM_ETH=y
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CONFIG_MVGBE=y
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CONFIG_MII=y
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CONFIG_PCI=y
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CONFIG_PCI_MVEBU=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_EMULATION=y
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CONFIG_SYS_NS16550=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PCI=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_JFFS2_LZO=y
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CONFIG_JFFS2_NAND=y
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56
include/configs/pogo_v4.h
Normal file
56
include/configs/pogo_v4.h
Normal file
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@ -0,0 +1,56 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014-2022 Tony Dinh <mibodhi@gmail.com>
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*
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* Based on
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* Copyright (C) 2012
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* David Purdy <david.c.purdy@gmail.com>
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*
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* Based on Kirkwood support:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#ifndef _CONFIG_POGO_V4_H
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#define _CONFIG_POGO_V4_H
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/*
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||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"dtb_file=/boot/dts/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"\
|
||||
"mtdids=nand0=orion_nand\0"\
|
||||
"bootargs_console=console=ttyS0,115200\0" \
|
||||
"bootcmd_usb=usb start; load usb 0:1 0x00800000 /boot/uImage; " \
|
||||
"load usb 0:1 0x01100000 /boot/uInitrd; " \
|
||||
"load usb 0:1 0x2c00000 $dtb_file\0"
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 0
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SATA Driver configuration
|
||||
*/
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
|
||||
/*
|
||||
* Support large disk for SATA and USB
|
||||
*/
|
||||
#define CONFIG_SYS_64BIT_LBA
|
||||
#define CONFIG_LBA48
|
||||
|
||||
#endif /* _CONFIG_POGO_V4_H */
|
||||
Loading…
Reference in New Issue
Block a user