sparc: Fix broken files during license changes
Fixes broken search and replaced license changes in
files cpu/leon3/start.S and include/asm/winmacro.h
from commit 1a4596601f
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
Series-to: u-boot
Series-cc: Tom Rini <trini@konsulko.com>
Series-version: 2
Cover-letter:
sparc: Updates to SPARC architecture in preperation for generic board
This patch series is a backlog of preparation work for upcomming
generic board changes.
I first want to get these reviewed and submitted to mainline before
sending out more patches.
END
This commit is contained in:
Francois Retief
Francois Retief
parent
9ac4fc8207
commit
72bcbd4bfb
@ -2,9 +2,6 @@
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* Copyright (C) 2007,
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* Copyright (C) 2007,
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* Daniel Hellstrom, daniel@gaisler.com
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* Daniel Hellstrom, daniel@gaisler.com
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*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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@ -136,130 +136,3 @@
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ld [reg + FW_FSR], %fsr;
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ld [reg + FW_FSR], %fsr;
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#endif
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#endif
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#ifndef __SPARC_WINMACRO_H__
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#define __SPARC_WINMACRO_H__
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#include <asm/asmmacro.h>
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#include <asm/stack.h>
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/* Store the register window onto the 8-byte aligned area starting
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* at %reg. It might be %sp, it might not, we don't care.
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*/
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#define RW_STORE(reg) \
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std %l0, [%reg + RW_L0]; \
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std %l2, [%reg + RW_L2]; \
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std %l4, [%reg + RW_L4]; \
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std %l6, [%reg + RW_L6]; \
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std %i0, [%reg + RW_I0]; \
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std %i2, [%reg + RW_I2]; \
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std %i4, [%reg + RW_I4]; \
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std %i6, [%reg + RW_I6];
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/* Load a register window from the area beginning at %reg. */
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#define RW_LOAD(reg) \
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ldd [%reg + RW_L0], %l0; \
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ldd [%reg + RW_L2], %l2; \
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ldd [%reg + RW_L4], %l4; \
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ldd [%reg + RW_L6], %l6; \
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ldd [%reg + RW_I0], %i0; \
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ldd [%reg + RW_I2], %i2; \
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ldd [%reg + RW_I4], %i4; \
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ldd [%reg + RW_I6], %i6;
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/* Loading and storing struct pt_reg trap frames. */
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#define PT_LOAD_INS(base_reg) \
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ldd [%base_reg + SF_REGS_SZ + PT_I0], %i0; \
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ldd [%base_reg + SF_REGS_SZ + PT_I2], %i2; \
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ldd [%base_reg + SF_REGS_SZ + PT_I4], %i4; \
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ldd [%base_reg + SF_REGS_SZ + PT_I6], %i6;
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#define PT_LOAD_GLOBALS(base_reg) \
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ld [%base_reg + SF_REGS_SZ + PT_G1], %g1; \
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ldd [%base_reg + SF_REGS_SZ + PT_G2], %g2; \
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ldd [%base_reg + SF_REGS_SZ + PT_G4], %g4; \
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ldd [%base_reg + SF_REGS_SZ + PT_G6], %g6;
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#define PT_LOAD_YREG(base_reg, scratch) \
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ld [%base_reg + SF_REGS_SZ + PT_Y], %scratch; \
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wr %scratch, 0x0, %y;
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#define PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
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ld [%base_reg + SF_REGS_SZ + PT_PSR], %pt_psr; \
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ld [%base_reg + SF_REGS_SZ + PT_PC], %pt_pc; \
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ld [%base_reg + SF_REGS_SZ + PT_NPC], %pt_npc;
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#define PT_LOAD_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
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PT_LOAD_YREG(base_reg, scratch) \
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PT_LOAD_INS(base_reg) \
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PT_LOAD_GLOBALS(base_reg) \
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PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
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#define PT_STORE_INS(base_reg) \
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std %i0, [%base_reg + SF_REGS_SZ + PT_I0]; \
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std %i2, [%base_reg + SF_REGS_SZ + PT_I2]; \
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std %i4, [%base_reg + SF_REGS_SZ + PT_I4]; \
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std %i6, [%base_reg + SF_REGS_SZ + PT_I6];
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#define PT_STORE_GLOBALS(base_reg) \
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st %g1, [%base_reg + SF_REGS_SZ + PT_G1]; \
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std %g2, [%base_reg + SF_REGS_SZ + PT_G2]; \
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std %g4, [%base_reg + SF_REGS_SZ + PT_G4]; \
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std %g6, [%base_reg + SF_REGS_SZ + PT_G6];
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#define PT_STORE_YREG(base_reg, scratch) \
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rd %y, %scratch; \
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st %scratch, [%base_reg + SF_REGS_SZ + PT_Y];
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#define PT_STORE_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
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st %pt_psr, [%base_reg + SF_REGS_SZ + PT_PSR]; \
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st %pt_pc, [%base_reg + SF_REGS_SZ + PT_PC]; \
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st %pt_npc, [%base_reg + SF_REGS_SZ + PT_NPC];
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#define PT_STORE_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
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PT_STORE_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
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PT_STORE_GLOBALS(base_reg) \
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PT_STORE_YREG(base_reg, g_scratch) \
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PT_STORE_INS(base_reg)
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/* Store the fpu register window*/
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#define FW_STORE(reg) \
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std %f0, [reg + FW_F0]; \
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std %f2, [reg + FW_F2]; \
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std %f4, [reg + FW_F4]; \
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std %f6, [reg + FW_F6]; \
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std %f8, [reg + FW_F8]; \
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std %f10, [reg + FW_F10]; \
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std %f12, [reg + FW_F12]; \
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std %f14, [reg + FW_F14]; \
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std %f16, [reg + FW_F16]; \
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std %f18, [reg + FW_F18]; \
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std %f20, [reg + FW_F20]; \
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std %f22, [reg + FW_F22]; \
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std %f24, [reg + FW_F24]; \
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std %f26, [reg + FW_F26]; \
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std %f28, [reg + FW_F28]; \
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std %f30, [reg + FW_F30]; \
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st %fsr, [reg + FW_FSR];
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/* Load a fpu register window from the area beginning at reg. */
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#define FW_LOAD(reg) \
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ldd [reg + FW_F0], %f0; \
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ldd [reg + FW_F2], %f2; \
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ldd [reg + FW_F4], %f4; \
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ldd [reg + FW_F6], %f6; \
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ldd [reg + FW_F8], %f8; \
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ldd [reg + FW_F10], %f10; \
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ldd [reg + FW_F12], %f12; \
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ldd [reg + FW_F14], %f14; \
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ldd [reg + FW_F16], %f16; \
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ldd [reg + FW_F18], %f18; \
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ldd [reg + FW_F20], %f20; \
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ldd [reg + FW_F22], %f22; \
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ldd [reg + FW_F24], %f24; \
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ldd [reg + FW_F26], %f26; \
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ldd [reg + FW_F28], %f28; \
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ldd [reg + FW_F30], %f30; \
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ld [reg + FW_FSR], %fsr;
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#endif
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