net: sh_eth: Fix 64bit build warnings
Fix various type warnings when building this driver for 64bit machine. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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@ -37,8 +37,8 @@
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#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
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!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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#define flush_cache_wback(addr, len) \
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flush_dcache_range((u32)addr, \
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(u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
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flush_dcache_range((unsigned long)addr, \
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(unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
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#else
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#define flush_cache_wback(...)
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#endif
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@ -46,11 +46,11 @@
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#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
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#define invalidate_cache(addr, len) \
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{ \
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u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
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u32 start, end; \
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unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
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unsigned long start, end; \
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\
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start = (u32)addr; \
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end = start + len; \
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start = (unsigned long)addr; \
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end = start + len; \
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start &= ~(line_size - 1); \
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end = ((end + line_size - 1) & ~(line_size - 1)); \
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\
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@ -74,7 +74,7 @@ static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
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}
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/* packet must be a 4 byte boundary */
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if ((int)packet & 3) {
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if ((uintptr_t)packet & 3) {
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printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
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, __func__);
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ret = -EFAULT;
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@ -211,7 +211,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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/* Make sure we use a P2 address (non-cacheable) */
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port_info->tx_desc_base =
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(struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
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(struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
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port_info->tx_desc_cur = port_info->tx_desc_base;
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/* Initialize all descriptors */
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@ -265,7 +265,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
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/* Make sure we use a P2 address (non-cacheable) */
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port_info->rx_desc_base =
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(struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
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(struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
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port_info->rx_desc_cur = port_info->rx_desc_base;
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@ -281,7 +281,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
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goto err_buf_alloc;
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}
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port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
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port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
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/* Initialize all descriptors */
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for (cur_rx_desc = port_info->rx_desc_base,
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@ -700,7 +700,7 @@ static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
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struct sh_ether_priv *priv = dev_get_priv(dev);
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struct sh_eth_dev *eth = &priv->shdev;
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
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uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
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int len;
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len = sh_eth_recv_start(eth);
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@ -850,7 +850,7 @@ static int sh_ether_probe(struct udevice *udev)
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eth->port = CONFIG_SH_ETHER_USE_PORT;
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eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
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eth->port_info[eth->port].iobase =
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(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
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(void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_enable(&priv->clk);
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@ -15,20 +15,20 @@
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#if defined(CONFIG_SH)
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/* Malloc returns addresses in the P1 area (cacheable). However we need to
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use area P2 (non-cacheable) */
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#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
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#define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
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/* The ethernet controller needs to use physical addresses */
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#if defined(CONFIG_SH_32BIT)
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#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
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#define ADDR_TO_PHY(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0x40000000))
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#else
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#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
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#define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
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#endif
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#elif defined(CONFIG_ARM)
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#ifndef inl
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#define inl readl
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#define outl writel
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#endif
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#define ADDR_TO_PHY(addr) ((int)(addr))
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#define ADDR_TO_PHY(addr) ((uintptr_t)(addr))
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#define ADDR_TO_P2(addr) (addr)
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#endif /* defined(CONFIG_SH) */
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