ADS5121 Add PATA support
Original patch from Ralph Kondziella
plus clean up by Wolfgang Denk
plus changes by John Rigby
use ips clock not lpc
port forward to current u-boot release
Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: John Rigby <jrigby@freescale.com>
This commit is contained in:
Ralph Kondziella
John Rigby
parent
abfbd0ae49
commit
70a4da45e1
@ -31,6 +31,8 @@
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#include <i2c.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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@ -38,6 +40,7 @@
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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@ -326,3 +329,104 @@ void ft_board_setup(void *blob, bd_t *bd)
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
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void init_ide_reset (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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debug ("init_ide_reset\n");
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/*
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* Clear the reset bit to reset the interface
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* cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
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*/
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immr->pata.pata_ata_control = 0;
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udelay(100);
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/* Assert the reset bit to enable the interface */
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immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
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udelay(100);
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}
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void ide_set_reset (int idereset)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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debug ("ide_set_reset(%d)\n", idereset);
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if (idereset) {
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immr->pata.pata_ata_control = 0;
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udelay(100);
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} else {
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immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
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udelay(100);
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}
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}
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#define CALC_TIMING(t) (t + period - 1) / period
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int ide_preinit (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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long t;
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const struct {
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short t0;
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short t1;
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short t2_8;
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short t2_16;
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short t2i;
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short t4;
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short t9;
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short tA;
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} pio_specs = {
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.t0 = 600,
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.t1 = 70,
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.t2_8 = 290,
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.t2_16 = 165,
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.t2i = 0,
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.t4 = 30,
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.t9 = 20,
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.tA = 50,
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};
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union {
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u32 config;
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struct {
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u8 field1;
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u8 field2;
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u8 field3;
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u8 field4;
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}bytes;
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}cfg;
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debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
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(u32)&immr->pata);
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/* Set the reset bit to 1 to enable the interface */
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immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
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/* Init timings : we use PIO mode 0 timings */
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t = 1000000000 / gd->ips_clk; /* period in ns */
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cfg.bytes.field1 = 3;
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cfg.bytes.field2 = 3;
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cfg.bytes.field3 = (pio_specs.t1 + t) / t;
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cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
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immr->pata.pata_time1 = cfg.config;
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cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
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cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
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cfg.bytes.field3 = 1;
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cfg.bytes.field4 = (pio_specs.t4 + t) / t;
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immr->pata.pata_time2 = cfg.config;
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cfg.config = immr->pata.pata_time3;
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cfg.bytes.field1 = (pio_specs.t9 + t) / t;
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immr->pata.pata_time3 = cfg.config;
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debug ("PATA preinit complete.\n");
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return 0;
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}
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#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
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@ -45,6 +45,10 @@
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#include <mpc5xxx.h>
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#endif
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#ifdef CONFIG_MPC512X
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#include <mpc512x.h>
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#endif
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#include <ide.h>
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#include <ata.h>
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@ -469,7 +469,34 @@ typedef struct lpc512x {
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* PATA
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*/
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typedef struct pata512x {
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u8 fixme[0x100];
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/* LOCAL Registers */
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u32 pata_time1; /* Time register 1: PIO and tx timing parameter */
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u32 pata_time2; /* Time register 2: PIO timing parameter */
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u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */
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u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */
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u32 pata_time5; /* Time register 5: UDMA timing parameter */
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u32 pata_time6; /* Time register 6: UDMA timing parameter */
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u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */
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u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */
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u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/
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u32 pata_ata_control; /* ATA Interface control register */
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u32 pata_irq_pending; /* Interrupt pending register (READONLY) */
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u32 pata_irq_enable; /* Interrupt enable register */
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u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/
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u32 pata_fifo_alarm; /* fifo alarm threshold */
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u32 res1[0x1A];
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/* DRIVE Registers */
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u32 pata_drive_data; /* drive data register*/
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u32 pata_drive_features;/* drive features register */
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u32 pata_drive_sectcnt; /* drive sector count register */
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u32 pata_drive_sectnum; /* drive sector number register */
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u32 pata_drive_cyllow; /* drive cylinder low register */
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u32 pata_drive_cylhigh; /* drive cylinder high register */
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u32 pata_drive_dev_head;/* drive device head register */
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u32 pata_drive_command; /* write = drive command, read = drive status reg */
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u32 res2[0x06];
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u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
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u32 res3[0x09];
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} pata512x_t;
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/*
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@ -355,11 +355,19 @@
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_DATE
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#undef CONFIG_CMD_FUSE
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_EXT2
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CONFIG_CMD_IDE)
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#define CONFIG_DOS_PARTITION
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#define CONFIG_MAC_PARTITION
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#define CONFIG_ISO_PARTITION
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#endif /* defined(CONFIG_CMD_IDE) */
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/*
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* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
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* For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
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@ -496,4 +504,48 @@
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for IDE not supported */
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#define CONFIG_IDE_RESET /* reset for IDE supported */
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA
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/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
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/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
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/* Interval between registers */
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#define CONFIG_SYS_ATA_STRIDE 4
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#define ATA_BASE_ADDR MPC512X_PATA
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/*
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* Control register bit definitions
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*/
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#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
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#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
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#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
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#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
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#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
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#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
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#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
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#define FSL_ATA_CTRL_IORDY_EN 0x01000000
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#endif /* __CONFIG_H */
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@ -573,6 +573,7 @@ void iopin_initialize(iopin_t *,int);
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/* Register Offset Base */
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#define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800)
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#define MPC512X_PATA (CONFIG_SYS_IMMR + 0x10200)
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/* IIM control */
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#define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5))
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