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4xx: Remove binary cpld bitstream from VOM405 board

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This patch removes the cpld binary bitstream that is
used by esd's cpld command on VOM405 boards.

Because u-boot with an external cpld bitstream may not
take more space in flash than before the u-boot binary is
shrinked a little bit.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs 2009-04-29 09:50:59 +02:00 committed by Wolfgang Denk
parent 0bb1063036
commit 700d553fd3
4 changed files with 6 additions and 1842 deletions
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8
board/esd/vom405/config.mk
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@ -20,10 +20,4 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# esd VOH405 boards
#
TEXT_BASE = 0xFFFC0000
#TEXT_BASE = 0x00FC0000
TEXT_BASE = 0xFFFC8000

1812
board/esd/vom405/fpgadata.c
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File diff suppressed because it is too large Load Diff

7
board/esd/vom405/vom405.c
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@ -31,13 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
extern void lxt971_no_sleep(void);
/* fpga configuration data - not compressed, generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};
int filesize = sizeof(fpgadata);
int board_early_init_f (void)
{
/*

21
include/configs/VOM405.h
View File

@ -177,10 +177,10 @@
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CONFIG_SYS_RAMBOOT 1
@ -231,8 +231,7 @@
/*
* FPGA stuff
*/
#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
@ -293,17 +292,7 @@
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#if 0
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
#endif
#if 0
#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
#endif
#if 1
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
#endif
#endif /* __CONFIG_H */