mpc83xx: initialize serdes for MPC837xEMDS boards
This patch is stolen from Anton Vorontsov's patch for mpc837xerdb boards. The reference clk and xcorevdd voltage of serdes1/2 is same between mpc837xemds and mpc837xerdb. 8377E: LYNX1- 2 SATA LYNX2- 2 PCIE 8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE 8379E: LYNX1- 2 SATA LYNX2- 2 SATA Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -12,6 +12,8 @@
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#include <common.h>
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#include <common.h>
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#include <i2c.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <spd_sdram.h>
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#include <spd_sdram.h>
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#if defined(CONFIG_OF_LIBFDT)
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <libfdt.h>
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@ -29,6 +31,37 @@ int board_early_init_f(void)
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/* Clear all of the interrupt of BCSR */
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/* Clear all of the interrupt of BCSR */
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bcsr[0xe] = 0xff;
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bcsr[0xe] = 0xff;
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#ifdef CONFIG_FSL_SERDES
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immap_t *immr = (immap_t *)CFG_IMMR;
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* we check only part num, and don't look for CPU revisions */
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switch (spridr >> 16) {
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case SPR_8379E_REV10 >> 16:
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case SPR_8379_REV10 >> 16:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378E_REV10 >> 16:
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case SPR_8378_REV10 >> 16:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8377E_REV10 >> 16:
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case SPR_8377_REV10 >> 16:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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default:
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printf("serdes not configured: unknown CPU part number: "
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"%04x\n", spridr >> 16);
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break;
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}
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#endif /* CONFIG_FSL_SERDES */
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return 0;
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return 0;
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}
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}
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@ -389,6 +389,11 @@
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/* Options are: TSEC[0-1] */
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_ETHPRIME "eTSEC1"
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/* SERDES */
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_FSL_SERDES2 0xe3100
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/*
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/*
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* Environment
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* Environment
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*/
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*/
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