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arm: rmobile: Add BLANCHE board support

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BLANCHE is development board based on R-Car V2H SoC (R8A7792)

This commit supports the following periherals:
- SCIF, Ethernet, QSPI, MMC

Signed-off-by: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
masakazu.mochizuki.wd@hitachi.com 2016-04-12 17:11:41 +09:00 committed by Nobuhiro Iwamatsu
parent 7593194685
commit 6f107e4cf6
19 changed files with 5006 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/mach-rmobile/Kconfig.32
View File

@ -7,6 +7,11 @@ choice
config TARGET_ARMADILLO_800EVA
bool "armadillo 800 eva board"
config TARGET_BLANCHE
bool "Blanche board"
select DM
select DM_SERIAL
config TARGET_GOSE
bool "Gose board"
select DM
@ -52,12 +57,12 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
default n
choice
prompt "Qos setting primary"
depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
depends on TARGET_ALT || TARGET_BLANCHE || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
default QOS_PRI_NORMAL
config QOS_PRI_NORMAL
@ -78,6 +83,7 @@ config QOS_PRI_GFX
endchoice
source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/renesas/blanche/Kconfig"
source "board/renesas/gose/Kconfig"
source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"

1
arch/arm/mach-rmobile/Makefile
View File

@ -13,6 +13,7 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o

1
arch/arm/mach-rmobile/cpu_info.c
View File

@ -53,6 +53,7 @@ static const struct {
{ 0x40, "R8A7740" },
{ 0x45, "R8A7790" },
{ 0x47, "R8A7791" },
{ 0x4A, "R8A7792" },
{ 0x4B, "R8A7793" },
{ 0x4C, "R8A7794" },
{ 0x0, "CPU" },

3
arch/arm/mach-rmobile/include/mach/gpio.h
View File

@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void);
#elif defined(CONFIG_R8A7791)
#include "r8a7791-gpio.h"
void r8a7791_pinmux_init(void);
#elif defined(CONFIG_R8A7792)
#include "r8a7792-gpio.h"
void r8a7792_pinmux_init(void);
#elif defined(CONFIG_R8A7793)
#include "r8a7793-gpio.h"
void r8a7793_pinmux_init(void);

220
arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h Normal file
View File

@ -0,0 +1,220 @@
#ifndef __ASM_R8A7792_GPIO_H__
#define __ASM_R8A7792_GPIO_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
*/
enum {
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
GPIO_GP_0_28,
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22,
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
GPIO_GP_3_28,
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
GPIO_GP_4_16,
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
GPIO_GP_5_16,
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
GPIO_GP_6_16,
GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
GPIO_GP_7_16,
GPIO_GP_8_0, GPIO_GP_8_1, GPIO_GP_8_2, GPIO_GP_8_3,
GPIO_GP_8_4, GPIO_GP_8_5, GPIO_GP_8_6, GPIO_GP_8_7,
GPIO_GP_8_8, GPIO_GP_8_9, GPIO_GP_8_10, GPIO_GP_8_11,
GPIO_GP_8_12, GPIO_GP_8_13, GPIO_GP_8_14, GPIO_GP_8_15,
GPIO_GP_8_16,
GPIO_GP_9_0, GPIO_GP_9_1, GPIO_GP_9_2, GPIO_GP_9_3,
GPIO_GP_9_4, GPIO_GP_9_5, GPIO_GP_9_6, GPIO_GP_9_7,
GPIO_GP_9_8, GPIO_GP_9_9, GPIO_GP_9_10, GPIO_GP_9_11,
GPIO_GP_9_12, GPIO_GP_9_13, GPIO_GP_9_14, GPIO_GP_9_15,
GPIO_GP_9_16,
GPIO_GP_10_0, GPIO_GP_10_1, GPIO_GP_10_2, GPIO_GP_10_3,
GPIO_GP_10_4, GPIO_GP_10_5, GPIO_GP_10_6, GPIO_GP_10_7,
GPIO_GP_10_8, GPIO_GP_10_9, GPIO_GP_10_10, GPIO_GP_10_11,
GPIO_GP_10_12, GPIO_GP_10_13, GPIO_GP_10_14, GPIO_GP_10_15,
GPIO_GP_10_16, GPIO_GP_10_17, GPIO_GP_10_18, GPIO_GP_10_19,
GPIO_GP_10_20, GPIO_GP_10_21, GPIO_GP_10_22, GPIO_GP_10_23,
GPIO_GP_10_24, GPIO_GP_10_25, GPIO_GP_10_26, GPIO_GP_10_27,
GPIO_GP_10_28, GPIO_GP_10_29, GPIO_GP_10_30, GPIO_GP_10_31,
GPIO_GP_11_0, GPIO_GP_11_1, GPIO_GP_11_2, GPIO_GP_11_3,
GPIO_GP_11_4, GPIO_GP_11_5, GPIO_GP_11_6, GPIO_GP_11_7,
GPIO_GP_11_8, GPIO_GP_11_9, GPIO_GP_11_10, GPIO_GP_11_11,
GPIO_GP_11_12, GPIO_GP_11_13, GPIO_GP_11_14, GPIO_GP_11_15,
GPIO_GP_11_16, GPIO_GP_11_17, GPIO_GP_11_18, GPIO_GP_11_19,
GPIO_GP_11_20, GPIO_GP_11_21, GPIO_GP_11_22, GPIO_GP_11_23,
GPIO_GP_11_24, GPIO_GP_11_25, GPIO_GP_11_26, GPIO_GP_11_27,
GPIO_GP_11_28, GPIO_GP_11_29,
GPIO_FN_DU1_DB2_C0_DATA12, GPIO_FN_DU1_DB3_C1_DATA13,
GPIO_FN_DU1_DB4_C2_DATA14, GPIO_FN_DU1_DB5_C3_DATA15,
GPIO_FN_DU1_DB6_C4, GPIO_FN_DU1_DB7_C5, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_DU1_DISP, GPIO_FN_DU1_CDE,
GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, GPIO_FN_D11,
GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, GPIO_FN_A0, GPIO_FN_A1,
GPIO_FN_A2, GPIO_FN_A3, GPIO_FN_A4, GPIO_FN_A5, GPIO_FN_A6, GPIO_FN_A7,
GPIO_FN_A8, GPIO_FN_A9, GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
GPIO_FN_A14, GPIO_FN_A15,
GPIO_FN_A16, GPIO_FN_A17, GPIO_FN_A18, GPIO_FN_A19,
GPIO_FN_CS1_A26, GPIO_FN_EX_CS0, GPIO_FN_EX_CS1, GPIO_FN_EX_CS2,
GPIO_FN_EX_CS3, GPIO_FN_EX_CS4, GPIO_FN_EX_CS5, GPIO_FN_BS,
GPIO_FN_RD, GPIO_FN_RD_WR, GPIO_FN_WE0, GPIO_FN_WE1, GPIO_FN_EX_WAIT0,
GPIO_FN_IRQ0, GPIO_FN_IRQ1, GPIO_FN_IRQ2, GPIO_FN_IRQ3, GPIO_FN_CS0,
GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_VSYNC,
GPIO_FN_VI0_D0_B0_C0, GPIO_FN_VI0_D1_B1_C1, GPIO_FN_VI0_D2_B2_C2, GPIO_FN_VI0_D3_B3_C3,
GPIO_FN_VI0_D4_B4_C4, GPIO_FN_VI0_D5_B5_C5, GPIO_FN_VI0_D6_B6_C6, GPIO_FN_VI0_D7_B7_C7,
GPIO_FN_VI0_D8_G0_Y0, GPIO_FN_VI0_D9_G1_Y1, GPIO_FN_VI0_D10_G2_Y2, GPIO_FN_VI0_D11_G3_Y3,
GPIO_FN_VI0_FIELD,
GPIO_FN_VI1_CLK, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_HSYNC,
GPIO_FN_VI1_VSYNC, GPIO_FN_VI1_D0_B0_C0, GPIO_FN_VI1_D1_B1_C1,
GPIO_FN_VI1_D2_B2_C2, GPIO_FN_VI1_D3_B3_C3, GPIO_FN_VI1_D4_B4_C4,
GPIO_FN_VI1_D5_B5_C5, GPIO_FN_VI1_D6_B6_C6, GPIO_FN_VI1_D7_B7_C7,
GPIO_FN_VI1_D8_G0_Y0, GPIO_FN_VI1_D9_G1_Y1, GPIO_FN_VI1_D10_G2_Y2,
GPIO_FN_VI1_D11_G3_Y3, GPIO_FN_VI1_FIELD,
GPIO_FN_VI3_D10_Y2, GPIO_FN_VI3_FIELD,
GPIO_FN_VI4_CLK,
GPIO_FN_VI5_CLK, GPIO_FN_VI5_D9_Y1, GPIO_FN_VI5_D10_Y2, GPIO_FN_VI5_D11_Y3, GPIO_FN_VI5_FIELD,
GPIO_FN_HRTS0, GPIO_FN_HCTS1, GPIO_FN_SCK0, GPIO_FN_CTS0, GPIO_FN_RTS0, GPIO_FN_TX0,
GPIO_FN_RX0, GPIO_FN_SCK1, GPIO_FN_CTS1, GPIO_FN_RTS1, GPIO_FN_TX1, GPIO_FN_RX1,
GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_TX, GPIO_FN_CAN0_RX,
GPIO_FN_CAN_CLK, GPIO_FN_CAN1_TX, GPIO_FN_CAN1_RX,
GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD, GPIO_FN_SD0_DAT0,
GPIO_FN_SD0_DAT1, GPIO_FN_SD0_DAT2, GPIO_FN_SD0_DAT3,
GPIO_FN_SD0_CD, GPIO_FN_SD0_WP, GPIO_FN_ADICLK,
GPIO_FN_ADICS_SAMP, GPIO_FN_ADIDATA, GPIO_FN_ADICHS0,
GPIO_FN_ADICHS1, GPIO_FN_ADICHS2, GPIO_FN_AVS1, GPIO_FN_AVS2,
GPIO_FN_DU0_DR0_DATA0, GPIO_FN_DU0_DR1_DATA1, GPIO_FN_DU0_DR2_Y4_DATA2,
GPIO_FN_DU0_DR3_Y5_DATA3, GPIO_FN_DU0_DR4_Y6_DATA4, GPIO_FN_DU0_DR5_Y7_DATA5,
GPIO_FN_DU0_DR6_Y8_DATA6, GPIO_FN_DU0_DR7_Y9_DATA7, GPIO_FN_DU0_DG0_DATA8,
GPIO_FN_DU0_DG1_DATA9, GPIO_FN_DU0_DG2_C6_DATA10, GPIO_FN_DU0_DG3_C7_DATA11,
GPIO_FN_DU0_DG4_Y0_DATA12, GPIO_FN_DU0_DG5_Y1_DATA13, GPIO_FN_DU0_DG6_Y2_DATA14,
GPIO_FN_DU0_DG7_Y3_DATA15, GPIO_FN_DU0_DB0, GPIO_FN_DU0_DB1,
GPIO_FN_DU0_DB2_C0, GPIO_FN_DU0_DB3_C1, GPIO_FN_DU0_DB4_C2,
GPIO_FN_DU0_DB5_C3, GPIO_FN_DU0_DB6_C4, GPIO_FN_DU0_DB7_C5,
GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_DU0_EXVSYNC_DU0_VSYNC,
GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_DU0_DISP, GPIO_FN_DU0_CDE,
GPIO_FN_DU1_DR2_Y4_DATA0, GPIO_FN_DU1_DR3_Y5_DATA1, GPIO_FN_DU1_DR4_Y6_DATA2,
GPIO_FN_DU1_DR5_Y7_DATA3, GPIO_FN_DU1_DR6_DATA4, GPIO_FN_DU1_DR7_DATA5,
GPIO_FN_DU1_DG2_C6_DATA6, GPIO_FN_DU1_DG3_C7_DATA7, GPIO_FN_DU1_DG4_Y0_DATA8,
GPIO_FN_DU1_DG5_Y1_DATA9, GPIO_FN_DU1_DG6_Y2_DATA10, GPIO_FN_DU1_DG7_Y3_DATA11,
GPIO_FN_A20, GPIO_FN_MOSI_IO0, GPIO_FN_A21, GPIO_FN_MISO_IO1, GPIO_FN_A22, GPIO_FN_IO2,
GPIO_FN_A23, GPIO_FN_IO3, GPIO_FN_A24, GPIO_FN_SPCLK, GPIO_FN_A25, GPIO_FN_SSL,
GPIO_FN_VI2_CLK, GPIO_FN_AVB_RX_CLK, GPIO_FN_VI2_CLKENB, GPIO_FN_AVB_RX_DV,
GPIO_FN_VI2_HSYNC, GPIO_FN_AVB_RXD0, GPIO_FN_VI2_VSYNC, GPIO_FN_AVB_RXD1,
GPIO_FN_VI2_D0_C0, GPIO_FN_AVB_RXD2, GPIO_FN_VI2_D1_C1, GPIO_FN_AVB_RXD3,
GPIO_FN_VI2_D2_C2, GPIO_FN_AVB_RXD4, GPIO_FN_VI2_D3_C3, GPIO_FN_AVB_RXD5,
GPIO_FN_VI2_D4_C4, GPIO_FN_AVB_RXD6, GPIO_FN_VI2_D5_C5, GPIO_FN_AVB_RXD7,
GPIO_FN_VI2_D6_C6, GPIO_FN_AVB_RX_ER, GPIO_FN_VI2_D7_C7, GPIO_FN_AVB_COL,
GPIO_FN_VI2_D8_Y0, GPIO_FN_AVB_TXD3, GPIO_FN_VI2_D9_Y1, GPIO_FN_AVB_TX_EN,
GPIO_FN_VI2_D10_Y2, GPIO_FN_AVB_TXD0, GPIO_FN_VI2_D11_Y3, GPIO_FN_AVB_TXD1,
GPIO_FN_VI2_FIELD, GPIO_FN_AVB_TXD2,
GPIO_FN_VI3_CLK, GPIO_FN_AVB_TX_CLK, GPIO_FN_VI3_CLKENB, GPIO_FN_AVB_TXD4,
GPIO_FN_VI3_HSYNC, GPIO_FN_AVB_TXD5, GPIO_FN_VI3_VSYNC, GPIO_FN_AVB_TXD6,
GPIO_FN_VI3_D0_C0, GPIO_FN_AVB_TXD7, GPIO_FN_VI3_D1_C1, GPIO_FN_AVB_TX_ER,
GPIO_FN_VI3_D2_C2, GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI3_D3_C3, GPIO_FN_AVB_MDC,
GPIO_FN_VI3_D4_C4, GPIO_FN_AVB_MDIO, GPIO_FN_VI3_D5_C5, GPIO_FN_AVB_LINK,
GPIO_FN_VI3_D6_C6, GPIO_FN_AVB_MAGIC, GPIO_FN_VI3_D7_C7, GPIO_FN_AVB_PHY_INT,
GPIO_FN_VI3_D8_Y0, GPIO_FN_AVB_CRS, GPIO_FN_VI3_D9_Y1, GPIO_FN_AVB_GTXREFCLK,
GPIO_FN_VI3_D11_Y3,
GPIO_FN_VI4_CLKENB, GPIO_FN_VI0_D12_G4_Y4, GPIO_FN_VI4_HSYNC, GPIO_FN_VI0_D13_G5_Y5,
GPIO_FN_VI4_VSYNC, GPIO_FN_VI0_D14_G6_Y6, GPIO_FN_VI4_D0_C0, GPIO_FN_VI0_D15_G7_Y7,
GPIO_FN_VI4_D1_C1, GPIO_FN_VI0_D16_R0, GPIO_FN_VI1_D12_G4_Y4_0,
GPIO_FN_VI4_D2_C2, GPIO_FN_VI0_D17_R1, GPIO_FN_VI1_D13_G5_Y5_0,
GPIO_FN_VI4_D3_C3, GPIO_FN_VI0_D18_R2, GPIO_FN_VI1_D14_G6_Y6_0,
GPIO_FN_VI4_D4_C4, GPIO_FN_VI0_D19_R3, GPIO_FN_VI1_D15_G7_Y7_0,
GPIO_FN_VI4_D5_C5, GPIO_FN_VI0_D20_R4, GPIO_FN_VI2_D12_Y4,
GPIO_FN_VI4_D6_C6, GPIO_FN_VI0_D21_R5, GPIO_FN_VI2_D13_Y5,
GPIO_FN_VI4_D7_C7, GPIO_FN_VI0_D22_R6, GPIO_FN_VI2_D14_Y6,
GPIO_FN_VI4_D8_Y0, GPIO_FN_VI0_D23_R7, GPIO_FN_VI2_D15_Y7,
GPIO_FN_VI4_D9_Y1, GPIO_FN_VI3_D12_Y4, GPIO_FN_VI4_D10_Y2, GPIO_FN_VI3_D13_Y5,
GPIO_FN_VI4_D11_Y3, GPIO_FN_VI3_D14_Y6, GPIO_FN_VI4_FIELD, GPIO_FN_VI3_D15_Y7,
GPIO_FN_VI5_CLKENB, GPIO_FN_VI1_D12_G4_Y4_1, GPIO_FN_VI5_HSYNC, GPIO_FN_VI1_D13_G5_Y5_1,
GPIO_FN_VI5_VSYNC, GPIO_FN_VI1_D14_G6_Y6_1, GPIO_FN_VI5_D0_C0, GPIO_FN_VI1_D15_G7_Y7_1,
GPIO_FN_VI5_D1_C1, GPIO_FN_VI1_D16_R0, GPIO_FN_VI5_D2_C2, GPIO_FN_VI1_D17_R1,
GPIO_FN_VI5_D3_C3, GPIO_FN_VI1_D18_R2, GPIO_FN_VI5_D4_C4, GPIO_FN_VI1_D19_R3,
GPIO_FN_VI5_D5_C5, GPIO_FN_VI1_D20_R4, GPIO_FN_VI5_D6_C6, GPIO_FN_VI1_D21_R5,
GPIO_FN_VI5_D7_C7, GPIO_FN_VI1_D22_R6, GPIO_FN_VI5_D8_Y0, GPIO_FN_VI1_D23_R7,
GPIO_FN_MSIOF0_SCK, GPIO_FN_HSCK0, GPIO_FN_MSIOF0_SYNC, GPIO_FN_HCTS0,
GPIO_FN_MSIOF0_TXD, GPIO_FN_HTX0, GPIO_FN_MSIOF0_RXD, GPIO_FN_HRX0,
GPIO_FN_MSIOF1_SCK, GPIO_FN_HSCK1, GPIO_FN_MSIOF1_SYNC, GPIO_FN_HRTS1,
GPIO_FN_MSIOF1_TXD, GPIO_FN_HTX1, GPIO_FN_MSIOF1_RXD, GPIO_FN_HRX1,
GPIO_FN_DRACK0, GPIO_FN_SCK2, GPIO_FN_DACK0, GPIO_FN_TX2,
GPIO_FN_DREQ0, GPIO_FN_RX2, GPIO_FN_DACK1, GPIO_FN_SCK3,
GPIO_FN_TX3, GPIO_FN_DREQ1, GPIO_FN_RX3,
GPIO_FN_PWM0, GPIO_FN_TCLK1, GPIO_FN_FSO_CFE_0,
GPIO_FN_PWM1, GPIO_FN_TCLK2, GPIO_FN_FSO_CFE_1,
GPIO_FN_PWM2, GPIO_FN_TCLK3, GPIO_FN_FSO_TOE,
GPIO_FN_PWM3, GPIO_FN_PWM4, GPIO_FN_SSI_SCK3, GPIO_FN_TPU0TO0,
GPIO_FN_SSI_WS3, GPIO_FN_TPU0TO1, GPIO_FN_SSI_SDATA3, GPIO_FN_TPU0TO2,
GPIO_FN_SSI_SCK4, GPIO_FN_TPU0TO3, GPIO_FN_SSI_WS4,
GPIO_FN_SSI_SDATA4, GPIO_FN_AUDIO_CLKOUT,
GPIO_FN_AUDIO_CLKA, GPIO_FN_AUDIO_CLKB,
};
#endif /* __ASM_R8A7792_GPIO_H__ */

34
arch/arm/mach-rmobile/include/mach/r8a7792.h Normal file
View File

@ -0,0 +1,34 @@
/*
* arch/arm/include/asm/arch-rmobile/r8a7792.h
*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7792_H
#define __ASM_ARCH_R8A7792_H
#include "rcar-base.h"
/* SH-I2C */
#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00400801
#define MSTP1_BITS 0x9B6F987F
#define MSTP2_BITS 0x108CE100
#define MSTP3_BITS 0x20004010
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0x44C00004
#define MSTP7_BITS 0x01BF0000
#define MSTP8_BITS 0x1FE01FB0
#define MSTP9_BITS 0xFE2BFFB2
#define MSTP10_BITS 0x00001820
#define MSTP11_BITS 0x00000008
/* SDHI */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
#endif /* __ASM_ARCH_R8A7792_H */

387
arch/arm/mach-rmobile/include/mach/rcar-base.h
View File

@ -10,7 +10,7 @@
#define __ASM_ARCH_RCAR_BASE_H
/*
* R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses
* R-Car (R8A7790/R8A7791/R8A7792/R8A7793/R8A7794) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
@ -142,6 +142,12 @@
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
#define SYS_AXI_AX2M_BASE 0xFF800380
#define SYS_AXI_CC50_BASE 0xFF8003C0
#define SYS_AXI_CCI_BASE 0xFF800440
#define SYS_AXI_CS_BASE 0xFF800480
#define SYS_AXI_DDM_BASE 0xFF8004C0
#define SYS_AXI_ETH_BASE 0xFF800500
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
@ -154,30 +160,49 @@
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
#define SYS_AXI_MPXM_BASE 0xFF800840
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define SYS_AXI_AX2M_BASE 0xFF800380
#define SYS_AXI_CC50_BASE 0xFF8003C0
#define SYS_AXI_CCI_BASE 0xFF800440
#define SYS_AXI_CS_BASE 0xFF800480
#define SYS_AXI_DDM_BASE 0xFF8004C0
#define SYS_AXI_ETH_BASE 0xFF800500
#define SYS_AXI_MPXM_BASE 0xFF800840
#define SYS_AXI_SAT0_BASE 0xFF800980
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define SYS_AXI_ADM_BASE 0xFF800D00
#define SYS_AXI_ADS_BASE 0xFF800D40
#define SYS_AXI_SYX_BASE 0xFF800FB8
#define SYS_AXI_AXI64TO128W_BASE 0xFF801300
#define SYS_AXI_AVBW_BASE 0xFF801340
#define SYS_AXI_CC50W_BASE 0xFF8013C0
#define SYS_AXI_CCIW_BASE 0xFF801440
#define SYS_AXI_CSW_BASE 0xFF801480
#define SYS_AXI_G2DW_BASE 0xFF801540
#define SYS_AXI_IMUX0W_BASE 0xFF801600
#define SYS_AXI_IMUX1W_BASE 0xFF801640
#define SYS_AXI_IMUX2W_BASE 0xFF801680
#define SYS_AXI_LBSW_BASE 0xFF8016C0
#define SYS_AXI_RTXW_BASE 0xFF801940
#define SYS_AXI_SDM0W_BASE 0xFF801A00
#define SYS_AXI_SDM1W_BASE 0xFF801A40
#define SYS_AXI_SDS0W_BASE 0xFF801A80
#define SYS_AXI_SDS1W_BASE 0xFF801AC0
#define SYS_AXI_TRABW_BASE 0xFF801B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
#define SYS_AXI_UDM0W_BASE 0xFF801B80
#define SYS_AXI_UDM1W_BASE 0xFF801BC0
#define SYS_AXI_ADMW_BASE 0xFF801D00
#define SYS_AXI_ADSW_BASE 0xFF801D40
#define SYS_AXI_SYXW_BASE 0xFF801FB8
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */
@ -186,6 +211,11 @@
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */
#define RT_AXI_RT_BASE 0xFF810FC0
#define RT_AXI_SHXW_BASE 0xFF811100
#define RT_AXI_DBGW_BASE 0xFF811140
#define RT_AXI_RTX64TO128W_BASE 0xFF811200
#define RT_AXI_RTW_BASE 0xFF811FC0
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
@ -197,8 +227,16 @@
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
#define SYS_AXI256_AXM_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
#define SYS_AXI256_IMP0_BASE 0xFF860580
#define SYS_AXI256_SY2_BASE 0xFF860FC0
#define SYS_AXI256_AXI128TO256W_BASE 0xFF861100
#define SYS_AXI256_AXMW_BASE 0xFF861140
#define SYS_AXI256_MXIW_BASE 0xFF8611C0
#define SYS_AXI256_IMP0W_BASE 0xFF861580
#define SYS_AXI256_SY2W_BASE 0xFF861FC0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
@ -227,9 +265,6 @@
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
@ -242,12 +277,6 @@
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
@ -261,8 +290,66 @@
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
#if defined (CONFIG_R8A7792)
#define MEDIA_AXI_VCTU0R_BASE 0xFE964500 /* R8A7792 */
#define MEDIA_AXI_VCTU0W_BASE 0xFE966500
#define MEDIA_AXI_VDCTU0R_BASE 0xFE964540
#define MEDIA_AXI_VDCTU0W_BASE 0xFE966540
#define MEDIA_AXI_VDCTU1R_BASE 0xFE964580
#define MEDIA_AXI_VDCTU1W_BASE 0xFE966580
#define MEDIA_AXI_VIN0W_BASE 0xFE967580
#define MEDIA_AXI_VIN1W_BASE 0xFE966D80
#define MEDIA_AXI_RDRW_BASE 0xFE9675C0
#define MEDIA_AXI_IMS01R_BASE 0xFE965500
#define MEDIA_AXI_IMS01W_BASE 0xFE967500
#define MEDIA_AXI_IMS23R_BASE 0xFE965540 /* FIXME */
#define MEDIA_AXI_IMS23W_BASE 0xFE967540
#define MEDIA_AXI_IMS45R_BASE 0xFE964D00
#define MEDIA_AXI_IMS45W_BASE 0xFE966D00
#define MEDIA_AXI_ROTCE4R_BASE 0xFE965100
#define MEDIA_AXI_ROTCE4W_BASE 0xFE967100
#define MEDIA_AXI_ROTVLC4R_BASE 0xFE965140
#define MEDIA_AXI_ROTVLC4W_BASE 0xFE965140
#define MEDIA_AXI_VSPD0R_BASE 0xFE964900
#define MEDIA_AXI_VSPD0W_BASE 0xFE966900
#define MEDIA_AXI_VSPD1R_BASE 0xFE964940
#define MEDIA_AXI_VSPD1W_BASE 0xFE966940
#define MEDIA_AXI_DU0R_BASE 0xFE964980
#define MEDIA_AXI_DU0W_BASE 0xFE966980
#define MEDIA_AXI_VSP0R_BASE 0xFE9649C0
#define MEDIA_AXI_VSP0W_BASE 0xFE9669C0
#define MEDIA_AXI_ROTCE0R_BASE 0xFE965900
#define MEDIA_AXI_ROTCE0W_BASE 0xFE967900
#define MEDIA_AXI_ROTVLC0R_BASE 0xFE965940
#define MEDIA_AXI_ROTVLC0W_BASE 0xFE967940
#define MEDIA_AXI_ROTCE1R_BASE 0xFE965980
#define MEDIA_AXI_ROTCE1W_BASE 0xFE967980
#define MEDIA_AXI_ROTVLC1R_BASE 0xFE9659C0
#define MEDIA_AXI_ROTVLC1W_BASE 0xFE9679C0
#define MEDIA_AXI_ROTCE2R_BASE 0xFE965D00
#define MEDIA_AXI_ROTCE2W_BASE 0xFE967D00
#define MEDIA_AXI_ROTVLC2R_BASE 0xFE965D40
#define MEDIA_AXI_ROTVLC2W_BASE 0xFE967D40
#define MEDIA_AXI_ROTCE3R_BASE 0xFE965D80
#define MEDIA_AXI_ROTCE3W_BASE 0xFE967D80
#define MEDIA_AXI_ROTVLC3R_BASE 0xFE965DC0
#define MEDIA_AXI_ROTVLC3W_BASE 0xFE967DC0
#else /* R8A7792 */
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#endif /* R8A7792 */
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_AX2MDMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
@ -301,6 +388,7 @@
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
#define SYS_AXI_AX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
@ -318,6 +406,11 @@
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
#define SYS_AXI_SAPC1SLVDMSCR 0xFF802154
#define SYS_AXI_SAPC2SLVDMSCR 0xFF802158
#define SYS_AXI_SAPC3SLVDMSCR 0xFF80215C
#define SYS_AXI_SAPC65SLVDMSCR 0xFF802160
#define SYS_AXI_SAPC8SLVDMSCR 0xFF802164
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
@ -325,8 +418,10 @@
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
#define SYS_AXI_SGXSLV1SLVDMSCR 0xFF802184
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
#define SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR 0xFF802190
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
@ -334,6 +429,32 @@
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
#define SYS_AXI_UTLBDSSLVDMSCR 0xFF8021B0
#define SYS_AXI_UTLBS0SLVDMSCR 0xFF8021B4
#define SYS_AXI_UTLBS1SLVDMSCR 0xFF8021B8
#define SYS_AXI_ROT0DMSCR 0xFF802320
#define SYS_AXI_ROT1DMSCR 0xFF802324
#define SYS_AXI_ROT2DMSCR 0xFF802328
#define SYS_AXI_ROT3DMSCR 0xFF80232C
#define SYS_AXI_ROT4DMSCR 0xFF802330
#define SYS_AXI_IMUX3SLVDMSCR 0xFF802334
#define SYS_AXI_STBR0SLVDMSCR 0xFF803200
#define SYS_AXI_STBR0PSLVDMSCR 0xFF803204
#define SYS_AXI_STBR0XSLVDMSCR 0xFF803208
#define SYS_AXI_STBR1SLVDMSCR 0xFF803210
#define SYS_AXI_STBR1PSLVDMSCR 0xFF803214
#define SYS_AXI_STBR1XSLVDMSCR 0xFF803218
#define SYS_AXI_STBR2SLVDMSCR 0xFF803220
#define SYS_AXI_STBR2PSLVDMSCR 0xFF803224
#define SYS_AXI_STBR2XSLVDMSCR 0xFF803228
#define SYS_AXI_STBR3SLVDMSCR 0xFF803230
#define SYS_AXI_STBR3PSLVDMSCR 0xFF803234
#define SYS_AXI_STBR3XSLVDMSCR 0xFF803238
#define SYS_AXI_STBR4SLVDMSCR 0xFF803240
#define SYS_AXI_STBR4PSLVDMSCR 0xFF803244
#define SYS_AXI_STBR4XSLVDMSCR 0xFF803248
#define SYS_AXI_ADM_DMSCR 0xFF803260
#define SYS_AXI_ADS_DMSCR 0xFF803264
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
@ -380,9 +501,86 @@
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
#define DM_AXI_DMAXICONF 0xFF850000
#define DM_AXI_DMAPBCONF 0xFF850004
#define DM_AXI_DMADMCONF 0xFF850020
#define DM_AXI_DMSDM0CONF 0xFF850024
#define DM_AXI_DMSDM1CONF 0xFF850028
#define DM_AXI_DMQSPAPSLVCONF 0xFF850030
#define DM_AXI_RAPD4SLVCONF 0xFF850034
#define DM_AXI_SAPD4SLVCONF 0xFF85003C
#define DM_AXI_SAPD5SLVCONF 0xFF850040
#define DM_AXI_SAPD6SLVCONF 0xFF850044
#define DM_AXI_SAPD65DSLVCONF 0xFF850048
#define DM_AXI_SDAP0SLVCONF 0xFF85004C
#define DM_AXI_MAPD2SLVCONF 0xFF850050
#define DM_AXI_MAPD3SLVCONF 0xFF850054
#define DM_AXI_DMXXDEFAULTSLAVESLVCONF 0xFF850058
#define DM_AXI_DMADMRQOSCONF 0xFF850100
#define DM_AXI_DMADMRQOSCTSET0 0xFF850104
#define DM_AXI_DMADMRQOSREQCTR 0xFF850114
#define DM_AXI_DMADMRQOSQON 0xFF850124
#define DM_AXI_DMADMRQOSIN 0xFF850128
#define DM_AXI_DMADMRQOSSTAT 0xFF85012C
#define DM_AXI_DMSDM0RQOSCONF 0xFF850140
#define DM_AXI_DMSDM0RQOSCTSET0 0xFF850144
#define DM_AXI_DMSDM0RQOSREQCTR 0xFF850154
#define DM_AXI_DMSDM0RQOSQON 0xFF850164
#define DM_AXI_DMSDM0RQOSIN 0xFF850168
#define DM_AXI_DMSDM0RQOSSTAT 0xFF85016C
#define DM_AXI_DMSDM1RQOSCONF 0xFF850180
#define DM_AXI_DMSDM1RQOSCTSET0 0xFF850184
#define DM_AXI_DMSDM1RQOSREQCTR 0xFF850194
#define DM_AXI_DMSDM1RQOSQON 0xFF8501A4
#define DM_AXI_DMSDM1RQOSIN 0xFF8501A8
#define DM_AXI_DMSDM1RQOSSTAT 0xFF8501AC
#define DM_AXI_DMRQOSCTSET1 0xFF850FC0
#define DM_AXI_DMRQOSCTSET2 0xFF850FC4
#define DM_AXI_DMRQOSCTSET3 0xFF850FC8
#define DM_AXI_DMRQOSTHRES0 0xFF850FCC
#define DM_AXI_DMRQOSTHRES1 0xFF850FD0
#define DM_AXI_DMRQOSTHRES2 0xFF850FD4
#define DM_AXI_DMADMWQOSCONF 0xFF851100
#define DM_AXI_DMADMWQOSCTSET0 0xFF851104
#define DM_AXI_DMADMWQOSREQCTR 0xFF851114
#define DM_AXI_DMADMWQOSQON 0xFF851124
#define DM_AXI_DMADMWQOSIN 0xFF851128
#define DM_AXI_DMADMWQOSSTAT 0xFF85112C
#define DM_AXI_DMSDM0WQOSCONF 0xFF851140
#define DM_AXI_DMSDM0WQOSCTSET0 0xFF851144
#define DM_AXI_DMSDM0WQOSREQCTR 0xFF851154
#define DM_AXI_DMSDM0WQOSQON 0xFF851164
#define DM_AXI_DMSDM0WQOSIN 0xFF851168
#define DM_AXI_DMSDM0WQOSSTAT 0xFF85116C
#define DM_AXI_DMSDM1WQOSCONF 0xFF851180
#define DM_AXI_DMSDM1WQOSCTSET0 0xFF851184
#define DM_AXI_DMSDM1WQOSREQCTR 0xFF851194
#define DM_AXI_DMSDM1WQOSQON 0xFF8511A4
#define DM_AXI_DMSDM1WQOSIN 0xFF8511A8
#define DM_AXI_DMSDM1WQOSSTAT 0xFF8511AC
#define DM_AXI_DMWQOSCTSET1 0xFF851FC0
#define DM_AXI_DMWQOSCTSET2 0xFF851FC4
#define DM_AXI_DMWQOSCTSET3 0xFF851FC8
#define DM_AXI_DMWQOSTHRES0 0xFF851FCC
#define DM_AXI_DMWQOSTHRES1 0xFF851FD0
#define DM_AXI_DMWQOSTHRES2 0xFF851FD4
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
#if defined(CONFIG_R8A7792)
#define DM_AXI_DMQSPAPSLVDMSCR 0xFF852104
#define DM_AXI_RAPD4SLVDMSCR 0xFF852108
#define DM_AXI_SAPD4SLVDMSCR 0xFF852110
#define DM_AXI_SAPD5SLVDMSCR 0xFF852114
#define DM_AXI_SAPD6SLVDMSCR 0xFF852118
#define DM_AXI_SAPD65DSLVDMSCR 0xFF85211C
#define DM_AXI_SDAP0SLVDMSCR 0xFF852120
#define DM_AXI_MAPD2SLVDMSCR 0xFF852124
#define DM_AXI_MAPD3SLVDMSCR 0xFF852128
#define DM_AXI_DMXXDEFAULTSLAVESLVDMSCR 0xFF85212C
#define DM_AXI_DMXREGDMSENN 0xFF852200
#else
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
@ -396,6 +594,7 @@
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
#endif
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
@ -407,6 +606,16 @@
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
#if defined(CONFIG_R8A7792)
#define MXT_IMRSLVDMSCR 0xFF872110
#define MXT_VINSLVDMSCR 0xFF872114
#define MXT_VSP1SLVDMSCR 0xFF87211C
#define MXT_VSPD0SLVDMSCR 0xFF872120
#define MXT_VSPD1SLVDMSCR 0xFF872124
#define MXT_MAP1SLVDMSCR 0xFF872128
#define MXT_MAP2SLVDMSCR 0xFF87212C
#define MXT_MAP2BSLVDMSCR 0xFF872134
#else /* R8A7792 */
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
@ -421,6 +630,58 @@
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
#endif /* R8A7792 */
/* DMS Register (MXI) */
#if defined(CONFIG_R8A7792)
#define MXI_JPURDMSCR 0xFE964200
#define MXI_JPUWDMSCR 0xFE966200
#define MXI_VCTU0RDMSCR 0xFE964600
#define MXI_VCTU0WDMSCR 0xFE966600
#define MXI_VDCTU0RDMSCR 0xFE964604
#define MXI_VDCTU0WDMSCR 0xFE966604
#define MXI_VDCTU1RDMSCR 0xFE964608
#define MXI_VDCTU1WDMSCR 0xFE966608
#define MXI_VIN0WDMSCR 0xFE967608
#define MXI_VIN1WDMSCR 0xFE966E08
#define MXI_RDRWDMSCR 0xFE96760C
#define MXI_IMS01RDMSCR 0xFE965600
#define MXI_IMS01WDMSCR 0xFE967600
#define MXI_IMS23RDMSCR 0xFE965604
#define MXI_IMS23WDMSCR 0xFE967604
#define MXI_IMS45RDMSCR 0xFE964E00
#define MXI_IMS45WDMSCR 0xFE966E00
#define MXI_IMRRDMSCR 0xFE964E04
#define MXI_IMRWDMSCR 0xFE966E04
#define MXI_ROTCE4RDMSCR 0xFE965200
#define MXI_ROTCE4WDMSCR 0xFE967200
#define MXI_ROTVLC4RDMSCR 0xFE965204
#define MXI_ROTVLC4WDMSCR 0xFE967204
#define MXI_VSPD0RDMSCR 0xFE964A00
#define MXI_VSPD0WDMSCR 0xFE966A00
#define MXI_VSPD1RDMSCR 0xFE964A04
#define MXI_VSPD1WDMSCR 0xFE966A04
#define MXI_DU0RDMSCR 0xFE964A08
#define MXI_DU0WDMSCR 0xFE966A08
#define MXI_VSP0RDMSCR 0xFE964A0C
#define MXI_VSP0WDMSCR 0xFE966A0C
#define MXI_ROTCE0RDMSCR 0xFE965A00
#define MXI_ROTCE0WDMSCR 0xFE967A00
#define MXI_ROTVLC0RDMSCR 0xFE965A04
#define MXI_ROTVLC0WDMSCR 0xFE967A04
#define MXI_ROTCE1RDMSCR 0xFE965A08
#define MXI_ROTCE1WDMSCR 0xFE967A08
#define MXI_ROTVLC1RDMSCR 0xFE965A0C
#define MXI_ROTVLC1WDMSCR 0xFE967A0C
#define MXI_ROTCE2RDMSCR 0xFE965E00
#define MXI_ROTCE2WDMSCR 0xFE967E00
#define MXI_ROTVLC2RDMSCR 0xFE965E04
#define MXI_ROTVLC2WDMSCR 0xFE967E04
#define MXI_ROTCE3RDMSCR 0xFE965E08
#define MXI_ROTCE3WDMSCR 0xFE967E08
#define MXI_ROTVLC3RDMSCR 0xFE965E0C
#define MXI_ROTVLC3WDMSCR 0xFE967E0C
#endif /* R8A7792 */
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
@ -597,6 +858,81 @@ struct rcar_dbsc3 {
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
u32 dummy17[27]; /* 0x394 .. 0x3FC */
u32 dbeccmode;
u32 dummy18[3]; /* 0x404 .. 0x40C */
u32 dbeccarea0;
u32 dbeccarea1;
u32 dbeccarea2;
u32 dbeccarea3;
u32 dummy19[4]; /* 0x420 .. 0x42C */
u32 dbeccintenable;
u32 dbeccintdetect;
u32 dummy20[22]; /* 0x438 .. 0x48C */
u32 dbeccmodulcnt;
u32 dummy21[27]; /* 0x494 .. 0x4FC */
u32 dbschecnt0;
u32 dummy22[63]; /* 0x504 .. 0x5FC */
u32 dbreradr0;
u32 dbreblane0;
u32 dbrerid0;
u32 dbrerinfo0;
u32 dbureradr0;
u32 dbureblane0;
u32 dburerid0;
u32 dburerinfo0;
u32 dbreradr1;
u32 dbreblane1;
u32 dbrerid1;
u32 dbrerinfo1;
u32 dbureradr1;
u32 dbureblane1;
u32 dburerid1;
u32 dburerinfo1;
u32 dbreradr2;
u32 dbreblane2;
u32 dbrerid2;
u32 dbrerinfo2;
u32 dbureradr2;
u32 dbureblane2;
u32 dburerid2;
u32 dburerinfo2;
u32 dbreradr3;
u32 dbreblane3;
u32 dbrerid3;
u32 dbrerinfo3;
u32 dbureradr3;
u32 dbureblane3;
u32 dburerid3;
u32 dburerinfo3;
u32 dummy23[160]; /* 0x680 .. 0x8FC */
u32 dbpccr;
u32 dbpeier;
u32 dbpeisr;
u32 dummy24;
u32 dbwdpesr0;
u32 dbwspesr0;
u32 dbpwear0;
u32 dbpweid0;
u32 dbpweinfo0;
u32 dummy25[3]; /* 0x924 .. 0x92C */
u32 dbwdpesr1;
u32 dbwspesr1;
u32 dbpwear1;
u32 dbpweid1;
u32 dbpweinfo1;
u32 dummy26[3]; /* 0x944 .. 0x94C */
u32 dbwdpesr2;
u32 dbwspesr2;
u32 dbpwear2;
u32 dbpweid2;
u32 dbpweinfo2;
u32 dummy27[3]; /* 0x964 .. 0x96C */
u32 dbwdpesr3;
u32 dbwspesr3;
u32 dbpwear3;
u32 dbpweid3;
u32 dbpweinfo3;
};
/* GPIO */
@ -678,6 +1014,10 @@ struct rcar_mxi {
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
u32 mxaxirtcr; /* R8a7792 only */
u32 mxaxiwtcr;
u32 mxs3crtcr;
u32 mxs3cwtcr;
};
struct rcar_mxi_qos {
@ -699,6 +1039,7 @@ struct rcar_axi_qos {
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
u32 qosin;
};
#endif

2
arch/arm/mach-rmobile/include/mach/rmobile.h
View File

@ -10,6 +10,8 @@
#include <asm/arch/r8a7790.h>
#elif defined(CONFIG_R8A7791)
#include <asm/arch/r8a7791.h>
#elif defined(CONFIG_R8A7792)
#include <asm/arch/r8a7792.h>
#elif defined(CONFIG_R8A7793)
#include <asm/arch/r8a7793.h>
#elif defined(CONFIG_R8A7794)

48
arch/arm/mach-rmobile/pfc-r8a7790.h
View File

@ -55,6 +55,54 @@
CPU_32_PORT(fn, pfx##_5_, sfx), \
CPU_32_PORT(fn, pfx##_6_, sfx), \
CPU_32_PORT1(fn, pfx##_7_, sfx)
#elif defined(CONFIG_R8A7792)
/*
* GP_0_0_DATA -> GP_11_29_DATA
* (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
* GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
*/
#define CPU_32_PORT0_28(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \
PORT_1(fn, pfx##28, sfx)
#define CPU_32_PORT0_22(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx)
#define CPU_32_PORT0_27(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
#define CPU_32_PORT0_16(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), \
PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
PORT_1(fn, pfx##16, sfx)
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT0_28(fn, pfx##_0_, sfx), \
CPU_32_PORT0_22(fn, pfx##_1_, sfx), \
CPU_32_PORT(fn, pfx##_2_, sfx), \
CPU_32_PORT0_27(fn, pfx##_3_, sfx), \
CPU_32_PORT0_16(fn, pfx##_4_, sfx), \
CPU_32_PORT0_16(fn, pfx##_5_, sfx), \
CPU_32_PORT0_16(fn, pfx##_6_, sfx), \
CPU_32_PORT0_16(fn, pfx##_7_, sfx), \
CPU_32_PORT0_16(fn, pfx##_8_, sfx), \
CPU_32_PORT0_16(fn, pfx##_9_, sfx), \
CPU_32_PORT(fn, pfx##_10_, sfx), \
CPU_32_PORT2(fn, pfx##_11_, sfx)
#else
#error "NO support"
#endif

2302
arch/arm/mach-rmobile/pfc-r8a7792.c Normal file
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File diff suppressed because it is too large Load Diff

12
board/renesas/blanche/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_BLANCHE
config SYS_BOARD
default "blanche"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "blanche"
endif

9
board/renesas/blanche/Makefile Normal file
View File

@ -0,0 +1,9 @@
#
# board/renesas/blanche/Makefile
#
# Copyright (C) 2016 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
obj-y := blanche.o qos.o ../rcar-common/common.o

458
board/renesas/blanche/blanche.c Normal file
View File

@ -0,0 +1,458 @@
/*
* board/renesas/blanche/blanche.c
* This file is blanche board support.
*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <miiphy.h>
#include <i2c.h>
#include <mmc.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
struct pin_db {
u32 addr; /* register address */
u32 mask; /* mask value */
u32 val; /* setting value */
};
#define PMMR 0xE6060000
#define GPSR10 0xE606002C
#define PUPR3 0xE606010C
#define PUPR10 0xE6060128
#define PUPR11 0xE606012C
#define CPG_PLL1CR 0xE6150028
#define CPG_PLL3CR 0xE61500DC
#define SetREG(x) \
writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
#define SetGuardREG(x) \
{ \
u32 val; \
val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
writel(~val, PMMR); \
writel(val, (x)->addr); \
}
struct pin_db pin_guard[] = {
{ GPSR10, 0xFFFFFFFF, 0x04006000 },
};
struct pin_db pin_tbl[] = {
{ PUPR3, 0xFFFFFFFF, 0x0803FF40 },
{ PUPR10, 0xFFFFFFFF, 0xC0438001 },
{ PUPR11, 0xFFFFFFFF, 0x0FC00007 },
};
void pin_init(void)
{
struct pin_db *db;
for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
SetGuardREG(db);
}
for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
SetREG(db);
}
}
#define s_init_wait(cnt) \
({ \
volatile u32 i = 0x10000 * cnt; \
while (i > 0) \
i--; \
})
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
u32 cpu_type;
cpu_type = rmobile_get_cpu_type();
if (cpu_type == 0x4A) {
writel(0x4D000000, CPG_PLL1CR);
writel(0x4F000000, CPG_PLL3CR);
}
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* QoS(Quality-of-Service) Init */
qos_init();
/* SCIF Init */
pin_init();
#if !defined(CONFIG_SYS_NO_FLASH)
struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
/* LBSC */
writel(0x00000020, &lbsc->cs0ctrl);
writel(0x00000020, &lbsc->cs1ctrl);
writel(0x00002020, &lbsc->ecs0ctrl);
writel(0x00002020, &lbsc->ecs1ctrl);
writel(0x2A103320, &lbsc->cswcr0);
writel(0x2A103320, &lbsc->cswcr1);
writel(0x19102110, &lbsc->ecswcr0);
writel(0x19102110, &lbsc->ecswcr1);
/* DBSC3 */
s_init_wait(10);
writel(0x0000A55A, &dbsc3_0->dbpdlck);
writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */
writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */
/* Stop Auto-Calibration */
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x80000000, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
/* PLLCR: PLL Control Register */
writel(0x00000006, &dbsc3_0->dbpdrga);
writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440
/* DXCCR: DATX8 Common Configuration Register */
writel(0x0000000F, &dbsc3_0->dbpdrga);
writel(0x00181EE4, &dbsc3_0->dbpdrgd);
/* DSGCR :DDR System General Configuration Register */
writel(0x00000010, &dbsc3_0->dbpdrga);
writel(0xF00464DB, &dbsc3_0->dbpdrgd);
writel(0x00000061, &dbsc3_0->dbpdrga);
writel(0x0000008D, &dbsc3_0->dbpdrgd);
/* Re-Execute ZQ calibration */
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000073, &dbsc3_0->dbpdrgd);
writel(0x00000007, &dbsc3_0->dbkind);
writel(0x0F030A02, &dbsc3_0->dbconf0);
writel(0x00000001, &dbsc3_0->dbphytype);
writel(0x00000000, &dbsc3_0->dbbl);
writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11
writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8
writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0
writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11
writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11
writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39
writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28
writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6
writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32
writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8
writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12
writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9
writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18
writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208
writel(0x00140005, &dbsc3_0->dbtr14);
writel(0x00050004, &dbsc3_0->dbtr15);
writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */
writel(0x000C0000, &dbsc3_0->dbtr17);
writel(0x00000300, &dbsc3_0->dbtr18);
writel(0x00000040, &dbsc3_0->dbtr19);
writel(0x00000001, &dbsc3_0->dbrnk0);
writel(0x00020001, &dbsc3_0->dbadj0);
writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */
writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */
writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
writel(0x00000011, &dbsc3_0->dbdficnt);
/* PGCR1 :PHY General Configuration Register 1 */
writel(0x00000003, &dbsc3_0->dbpdrga);
writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */
/* PGCR2: PHY General Configuration Registers 2 */
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
writel(0x00000011, &dbsc3_0->dbpdrga);
writel(0x1000040B, &dbsc3_0->dbpdrgd);
/* DTPR0 :DRAM Timing Parameters Register 0 */
writel(0x00000012, &dbsc3_0->dbpdrga);
writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
/* DTPR1 :DRAM Timing Parameters Register 1 */
writel(0x00000013, &dbsc3_0->dbpdrga);
writel(0x1A868400, &dbsc3_0->dbpdrgd);
/* DTPR2 ::DRAM Timing Parameters Register 2 */
writel(0x00000014, &dbsc3_0->dbpdrga);
writel(0x300214D8, &dbsc3_0->dbpdrgd);
/* MR0 :Mode Register 0 */
writel(0x00000015, &dbsc3_0->dbpdrga);
writel(0x00000D70, &dbsc3_0->dbpdrgd);
/* MR1 :Mode Register 1 */
writel(0x00000016, &dbsc3_0->dbpdrga);
writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */
/* MR2 :Mode Register 2 */
writel(0x00000017, &dbsc3_0->dbpdrga);
writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */
/* VREF(ZQCAL) */
writel(0x0000001A, &dbsc3_0->dbpdrga);
writel(0x910035C7, &dbsc3_0->dbpdrgd);
/* PGSR0 :PHY General Status Registers 0 */
writel(0x00000004, &dbsc3_0->dbpdrga);
while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
/* DRAM Init (set MRx etc) */
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000181, &dbsc3_0->dbpdrgd);
/* CKE = H */
writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
/* PGSR0 :PHY General Status Registers 0 */
writel(0x00000004, &dbsc3_0->dbpdrga);
while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
/* RAM ACC Training */
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x0000FE01, &dbsc3_0->dbpdrgd);
/* Bus control 0 */
writel(0x00000000, &dbsc3_0->dbbs0cnt1);
/* DDR3 Calibration set */
writel(0x01004C20, &dbsc3_0->dbcalcnf);
/* DDR3 Calibration timing */
writel(0x014000AA, &dbsc3_0->dbcaltr);
/* Refresh */
writel(0x00000140, &dbsc3_0->dbrfcnf0);
writel(0x00081860, &dbsc3_0->dbrfcnf1);
writel(0x00010000, &dbsc3_0->dbrfcnf2);
/* PGSR0 :PHY General Status Registers 0 */
writel(0x00000004, &dbsc3_0->dbpdrga);
while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
/* Enable Auto-Refresh */
writel(0x00000001, &dbsc3_0->dbrfen);
/* Permit DDR-Access */
writel(0x00000001, &dbsc3_0->dbacen);
/* This locks the access to the PHY unit registers */
writel(0x00000000, &dbsc3_0->dbpdlck);
#endif /* CONFIG_SYS_NO_FLASH */
}
#define TMU0_MSTP125 (1 << 25)
#define SCIF0_MSTP721 (1 << 21)
#define SDHI0_MSTP314 (1 << 14)
#define QSPI_MSTP917 (1 << 17)
int board_early_init_f(void)
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
/* SCIF0 */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* SDHI0 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
/* QSPI */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
/* Init PFC controller */
r8a7792_pinmux_init();
gpio_request(GPIO_FN_D0, NULL);
gpio_request(GPIO_FN_D1, NULL);
gpio_request(GPIO_FN_D2, NULL);
gpio_request(GPIO_FN_D3, NULL);
gpio_request(GPIO_FN_D4, NULL);
gpio_request(GPIO_FN_D5, NULL);
gpio_request(GPIO_FN_D6, NULL);
gpio_request(GPIO_FN_D7, NULL);
gpio_request(GPIO_FN_D8, NULL);
gpio_request(GPIO_FN_D9, NULL);
gpio_request(GPIO_FN_D10, NULL);
gpio_request(GPIO_FN_D11, NULL);
gpio_request(GPIO_FN_D12, NULL);
gpio_request(GPIO_FN_D13, NULL);
gpio_request(GPIO_FN_D14, NULL);
gpio_request(GPIO_FN_D15, NULL);
gpio_request(GPIO_FN_A0, NULL);
gpio_request(GPIO_FN_A1, NULL);
gpio_request(GPIO_FN_A2, NULL);
gpio_request(GPIO_FN_A3, NULL);
gpio_request(GPIO_FN_A4, NULL);
gpio_request(GPIO_FN_A5, NULL);
gpio_request(GPIO_FN_A6, NULL);
gpio_request(GPIO_FN_A7, NULL);
gpio_request(GPIO_FN_A8, NULL);
gpio_request(GPIO_FN_A9, NULL);
gpio_request(GPIO_FN_A10, NULL);
gpio_request(GPIO_FN_A11, NULL);
gpio_request(GPIO_FN_A12, NULL);
gpio_request(GPIO_FN_A13, NULL);
gpio_request(GPIO_FN_A14, NULL);
gpio_request(GPIO_FN_A15, NULL);
gpio_request(GPIO_FN_A16, NULL);
gpio_request(GPIO_FN_A17, NULL);
gpio_request(GPIO_FN_A18, NULL);
gpio_request(GPIO_FN_A19, NULL);
#if defined(CONFIG_SYS_NO_FLASH)
gpio_request(GPIO_FN_MOSI_IO0, NULL);
gpio_request(GPIO_FN_MISO_IO1, NULL);
gpio_request(GPIO_FN_IO2, NULL);
gpio_request(GPIO_FN_IO3, NULL);
gpio_request(GPIO_FN_SPCLK, NULL);
gpio_request(GPIO_FN_SSL, NULL);
#else /* CONFIG_SYS_NO_FLASH */
gpio_request(GPIO_FN_A20, NULL);
gpio_request(GPIO_FN_A21, NULL);
gpio_request(GPIO_FN_A22, NULL);
gpio_request(GPIO_FN_A23, NULL);
gpio_request(GPIO_FN_A24, NULL);
gpio_request(GPIO_FN_A25, NULL);
#endif /* CONFIG_SYS_NO_FLASH */
gpio_request(GPIO_FN_CS1_A26, NULL);
gpio_request(GPIO_FN_EX_CS0, NULL);
gpio_request(GPIO_FN_EX_CS1, NULL);
gpio_request(GPIO_FN_BS, NULL);
gpio_request(GPIO_FN_RD, NULL);
gpio_request(GPIO_FN_WE0, NULL);
gpio_request(GPIO_FN_WE1, NULL);
gpio_request(GPIO_FN_EX_WAIT0, NULL);
gpio_request(GPIO_FN_IRQ0, NULL);
gpio_request(GPIO_FN_IRQ2, NULL);
gpio_request(GPIO_FN_IRQ3, NULL);
gpio_request(GPIO_FN_CS0, NULL);
/* Init timer */
timer_init();
return 0;
}
/*
Added for BLANCHE(R-CarV2H board)
*/
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
#define STR_ENV_ETHADDR "ethaddr"
struct eth_device *dev;
uchar eth_addr[6];
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
dev = eth_get_dev_by_index(0);
if (dev) {
eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
} else {
printf("blanche: Couldn't get eth device\n");
rc = -1;
}
}
#endif
return rc;
}
int board_mmc_init(bd_t *bis)
{
int ret = -ENODEV;
#ifdef CONFIG_SH_SDHI
gpio_request(GPIO_FN_SD0_DAT0, NULL);
gpio_request(GPIO_FN_SD0_DAT1, NULL);
gpio_request(GPIO_FN_SD0_DAT2, NULL);
gpio_request(GPIO_FN_SD0_DAT3, NULL);
gpio_request(GPIO_FN_SD0_CLK, NULL);
gpio_request(GPIO_FN_SD0_CMD, NULL);
gpio_request(GPIO_FN_SD0_CD, NULL);
gpio_request(GPIO_GP_11_12, NULL);
gpio_direction_output(GPIO_GP_11_12, 1); /* power on */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
SH_SDHI_QUIRK_16BIT_BUF);
if (ret)
return ret;
#endif
return ret;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
};
void reset_cpu(ulong addr)
{
}
static const struct sh_serial_platdata serial_platdata = {
.base = SCIF0_BASE,
.type = PORT_SCIF,
.clk = 14745600,
.clk_mode = EXT_CLK,
};
U_BOOT_DEVICE(blanche_serials) = {
.name = "serial_sh",
.platdata = &serial_platdata,
};

1366
board/renesas/blanche/qos.c Normal file
View File

File diff suppressed because it is too large Load Diff

12
board/renesas/blanche/qos.h Normal file
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@ -0,0 +1,12 @@
/*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __QOS_H__
#define __QOS_H__
void qos_init(void);
#endif

22
configs/blanche_defconfig Normal file
View File

@ -0,0 +1,22 @@
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_BLANCHE=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y

32
drivers/mmc/sh_sdhi.c
View File

@ -399,7 +399,6 @@ static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
{
unsigned short i, j, cnt = 1;
unsigned short resp[8];
unsigned long *p1, *p2;
if (cmd->resp_type & MMC_RSP_136) {
cnt = 4;
@ -418,30 +417,29 @@ static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
resp[i] |= (resp[j--] >> 8) & 0x00ff;
}
resp[0] = (resp[0] << 8) & 0xff00;
/* SDHI REGISTER SPECIFICATION */
p1 = ((unsigned long *)resp) + 3;
} else {
resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
p1 = ((unsigned long *)resp);
}
p2 = (unsigned long *)cmd->response;
barrier();
#if defined(__BIG_ENDIAN_BITFIELD)
for (i = 0; i < cnt; i++) {
*p2++ = ((*p1 >> 16) & 0x0000ffff) |
((*p1 << 16) & 0xffff0000);
p1--;
if (cnt == 4) {
cmd->response[0] = (resp[6] << 16) | resp[7];
cmd->response[1] = (resp[4] << 16) | resp[5];
cmd->response[2] = (resp[2] << 16) | resp[3];
cmd->response[3] = (resp[0] << 16) | resp[1];
} else {
cmd->response[0] = (resp[0] << 16) | resp[1];
}
#else
for (i = 0; i < cnt; i++)
*p2++ = *p1--;
if (cnt == 4) {
cmd->response[0] = (resp[7] << 16) | resp[6];
cmd->response[1] = (resp[5] << 16) | resp[4];
cmd->response[2] = (resp[3] << 16) | resp[2];
cmd->response[3] = (resp[1] << 16) | resp[0];
} else {
cmd->response[0] = (resp[1] << 16) | resp[0];
}
#endif /* __BIG_ENDIAN_BITFIELD */
}

10
drivers/serial/serial_sh.h
View File

@ -225,8 +225,8 @@ struct uart_port {
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \
defined(CONFIG_R8A7795)
defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795)
# if defined(CONFIG_SCIF_A)
# define SCIF_ORER 0x0200
# else
@ -308,7 +308,7 @@ struct uart_port {
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# if defined(CONFIG_SCIF_A)
@ -566,7 +566,7 @@ SCIF_FNS(SCFCR, 0x18, 16)
SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCLSR, 0x24, 16)
SCIF_FNS(DL, 0x00, 0) /* dummy */
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
/* SCIFA and SCIF register offsets and size */
SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
@ -762,7 +762,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
#if defined(CONFIG_SCIF_A)

124
include/configs/blanche.h Executable file
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@ -0,0 +1,124 @@
/*
* include/configs/blanche.h
* This file is blanche board configuration.
*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __BLANCHE_H
#define __BLANCHE_H
#undef DEBUG
#define CONFIG_R8A7792
#define CONFIG_RMOBILE_BOARD_STRING "Blanche"
#include "rcar-gen2-common.h"
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC
#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE 0x40000000
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF0
#define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024)
#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
/* FLASH */
/* #define CONFIG_SYS_NO_FLASH */ /* uncomment if use QSPI-FLASH */
#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_SPI
#define CONFIG_SH_QSPI
#define CONFIG_SH_QSPI_BASE 0xE6B10000
#else
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
#define CONFIG_CMD_FLASH
#undef CONFIG_CMD_SF
#undef CONFIG_CMD_SPI
#endif
/* BLANCHE on board LANC: SMC89218 (ExCS0) */
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_16_BIT 1
#define CONFIG_SMC911X_BASE 0x18000000
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_SYS_TMU_CLK_DIV 4
/* ENV setting */
#if defined(CONFIG_SYS_NO_FLASH)
#else
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#undef CONFIG_ENV_ADDR
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
#endif
/* USB */
#undef CONFIG_CMD_USB
/* MMC */
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* SDHI0 */
#define CONFIG_SMSTP3_ENA 0x00004000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA 0x00200000
/* QSPI */
#define CONFIG_SMSTP9_ENA 0x00020000
/* SYS-DMAC0 */
#define CONFIG_RMSTP2_ENA 0x00080000
/* SDHI */
#define CONFIG_SH_SDHI_FREQ 97500000
#endif /* __BLANCHE_H */