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Merge git://www.denx.de/git/u-boot-imx

Browse Source 
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2017-11-27 07:22:11 -05:00
commit 6e6cf015e7
97 changed files with 2162 additions and 1027 deletions
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7
README
View File

@ -2362,6 +2362,13 @@ The following options need to be configured:
CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
the bootcounter.
CONFIG_BOOTCOUNT_ALEN = address len
CONFIG_BOOTCOUNT_EXT
enable support for the bootcounter in EXT filesystem
CONFIG_SYS_BOOTCOUNT_ADDR = RAM address used for read
and write.
CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE = interface
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART = device and part
CONFIG_SYS_BOOTCOUNT_EXT_NAME = filename
- Show boot progress:
CONFIG_SHOW_BOOT_PROGRESS

7
arch/arm/dts/imx6qdl-icore-rqs.dtsi
View File

@ -43,6 +43,11 @@
#include <dt-bindings/clock/imx6qdl-clock.h>
/ {
aliases {
mmc1 = &usdhc3;
mmc2 = &usdhc4;
};
memory {
reg = <0x10000000 0x80000000>;
};
@ -100,6 +105,7 @@
};
&usdhc3 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@ -165,6 +171,7 @@
};
pinctrl_usdhc3: usdhc3grp {
u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070

2
arch/arm/dts/imx6qdl-icore.dtsi
View File

@ -118,6 +118,7 @@
};
&usdhc1 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@ -208,6 +209,7 @@
};
pinctrl_usdhc1: usdhc1grp {
u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070

5
arch/arm/dts/imx6qdl.dtsi
View File

@ -77,6 +77,7 @@
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
u-boot,dm-spl;
dma_apbh: dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@ -225,6 +226,7 @@
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
@ -516,6 +518,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
@ -805,6 +808,7 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
u-boot,dm-spl;
};
ldb: ldb@020e0008 {
@ -889,6 +893,7 @@
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
u-boot,dm-spl;
crypto: caam@2100000 {
compatible = "fsl,sec-v4.0";

4
arch/arm/dts/imx6ul-geam-kit.dts
View File

@ -87,6 +87,7 @@
};
&usdhc1 {
u-boot,dm-spl;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@ -134,6 +135,7 @@
};
pinctrl_usdhc1: usdhc1grp {
u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
@ -145,6 +147,7 @@
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@ -156,6 +159,7 @@
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9

2
arch/arm/dts/imx6ul-isiot-emmc.dts
View File

@ -50,6 +50,7 @@
};
&usdhc2 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
@ -60,6 +61,7 @@
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070

2
arch/arm/dts/imx6ul-isiot.dtsi
View File

@ -82,6 +82,7 @@
};
&usdhc1 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
@ -128,6 +129,7 @@
};
pinctrl_usdhc1: usdhc1grp {
u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059

6
arch/arm/dts/imx6ul.dtsi
View File

@ -134,6 +134,7 @@
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
u-boot,dm-spl;
pmu {
compatible = "arm,cortex-a7-pmu";
@ -185,6 +186,7 @@
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
@ -415,6 +417,7 @@
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
<&iomuxc 16 33 16>;
u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
@ -451,6 +454,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
u-boot,dm-spl;
};
gpio5: gpio@020ac000 {
@ -649,6 +653,7 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
u-boot,dm-spl;
};
gpr: iomuxc-gpr@020e4000 {
@ -729,6 +734,7 @@
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
u-boot,dm-spl;
usbotg1: usb@02184000 {
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";

8
arch/arm/include/asm/arch-mx5/crm_regs.h
View File

@ -210,6 +210,14 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
/* Define the bits in register CSCMR2 */
#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26
#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26)
#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26)
#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7)
#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)

50
arch/arm/include/asm/arch-mx5/imx-regs.h
View File

@ -416,6 +416,39 @@ struct iomuxc {
};
#endif
#define IOMUXC_GPR2_BITMAP_SPWG 0
#define IOMUXC_GPR2_BITMAP_JEIDA 1
#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \
IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \
IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_18 0
#define IOMUXC_GPR2_DATA_WIDTH_24 1
#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \
IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \
IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
#define IOMUXC_GPR2_MODE_DISABLED 0
#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
/* System Reset Controller (SRC) */
struct src {
u32 scr;
@ -508,6 +541,23 @@ struct fuse_bank4_regs {
};
#endif
#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
#define PWMCR_DOZEEN (1 << 24)
#define PWMCR_WAITEN (1 << 23)
#define PWMCR_DBGEN (1 << 22)
#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
#define PWMCR_CLKSRC_IPG (1 << 16)
#define PWMCR_EN (1 << 0)
struct pwm_regs {
u32 cr;
u32 sr;
u32 ir;
u32 sar;
u32 pr;
u32 cnr;
};
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */

2
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -367,7 +367,7 @@
#include <asm/types.h>
/* only for i.MX6SX/UL */
#define WDOG3_BASE_ADDR ((is_mx6ul() ? \
#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
MX6SLL_LCDIF_BASE_ADDR : \

2
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -105,7 +105,7 @@ void set_chipselect_size(int const);
void init_aips(void);
void init_src(void);
void imx_set_wdog_powerdown(bool enable);
void imx_wdog_disable_powerdown(void);
int board_mmc_get_env_dev(int devno);

12
arch/arm/mach-imx/init.c
View File

@ -65,7 +65,7 @@ void init_aips(void)
}
}
void imx_set_wdog_powerdown(bool enable)
void imx_wdog_disable_powerdown(void)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
@ -75,13 +75,13 @@ void imx_set_wdog_powerdown(bool enable)
#endif
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
writew(0, &wdog1->wmcr);
writew(0, &wdog2->wmcr);
if (is_mx6sx() || is_mx6ul() || is_mx7())
writew(enable, &wdog3->wmcr);
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
writew(0, &wdog3->wmcr);
#ifdef CONFIG_MX7D
writew(enable, &wdog4->wmcr);
writew(0, &wdog4->wmcr);
#endif
}

7
arch/arm/mach-imx/mx5/Kconfig
View File

@ -46,6 +46,12 @@ config TARGET_MX53LOCO
select BOARD_LATE_INIT
select MX53
config TARGET_MX53PPD
bool "Support mx53ppd"
select MX53
help
Enable support for the GE Healthcare PPD.
config TARGET_MX53SMD
bool "Support mx53smd"
select MX53
@ -70,6 +76,7 @@ source "board/freescale/mx53ard/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
source "board/technologic/ts4800/Kconfig"

60
arch/arm/mach-imx/mx6/Kconfig
View File

@ -109,6 +109,7 @@ config TARGET_ARISTAINETOS2B
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
@ -117,6 +118,7 @@ config TARGET_CGTQMX6EVAL
config TARGET_CM_FX6
bool "CM-FX6"
select SUPPORT_SPL
select MX6QDL
select DM
select DM_SERIAL
select DM_GPIO
@ -131,6 +133,7 @@ config TARGET_COLIBRI_IMX6
config TARGET_DHCOMIMX6
bool "dh_imx6"
select MX6QDL
select BOARD_LATE_INIT
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
@ -165,6 +168,7 @@ config TARGET_GE_B850V3
config TARGET_GW_VENTANA
bool "gw_ventana"
select MX6QDL
select SUPPORT_SPL
imply CMD_SATA
imply CMD_SPL
@ -176,10 +180,12 @@ config TARGET_KOSAGI_NOVENA
config TARGET_MCCMON6
bool "mccmon6"
select MX6QDL
select SUPPORT_SPL
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
@ -199,23 +205,8 @@ config TARGET_MX6LOGICPD
config TARGET_MX6QARM2
bool "mx6qarm2"
config TARGET_MX6Q_ICORE
bool "Support Engicam i.Core"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select SPL_OF_LIBFDT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
config TARGET_MX6Q_ICORE_RQS
bool "Support Engicam i.Core RQS"
config TARGET_MX6Q_ENGICAM
bool "Support Engicam i.Core(RQS)"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
@ -228,9 +219,14 @@ config TARGET_MX6Q_ICORE_RQS
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
@ -239,6 +235,7 @@ config TARGET_MX6SABREAUTO
config TARGET_MX6SABRESD
bool "mx6sabresd"
select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
@ -288,20 +285,8 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
config TARGET_MX6UL_GEAM
bool "Support Engicam GEAM6UL"
select BOARD_LATE_INIT
select MX6UL
select OF_CONTROL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
config TARGET_MX6UL_ISIOT
bool "Support Engicam Is.IoT MX6UL"
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
select BOARD_LATE_INIT
select MX6UL
select OF_CONTROL
@ -312,6 +297,10 @@ config TARGET_MX6UL_ISIOT
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
@ -360,6 +349,7 @@ config TARGET_PCM058
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
@ -378,6 +368,7 @@ config TARGET_TQMA6
config TARGET_UDOO
bool "udoo"
select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
@ -398,6 +389,7 @@ config TARGET_SAMTEC_VINING_2000
config TARGET_WANDBOARD
bool "wandboard"
select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
@ -446,10 +438,8 @@ source "board/congatec/cgtqmx6eval/Kconfig"
source "board/dhelectronics/dh_imx6/Kconfig"
source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/engicam/geam6ul/Kconfig"
source "board/engicam/icorem6/Kconfig"
source "board/engicam/icorem6_rqs/Kconfig"
source "board/engicam/isiotmx6ul/Kconfig"
source "board/engicam/imx6q/Kconfig"
source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6sabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"

2
arch/arm/mach-imx/mx6/soc.c
View File

@ -436,7 +436,7 @@ int arch_cpu_init(void)
if (is_mx6sl())
setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
if (is_mx6sx())
setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);

2
arch/arm/mach-imx/mx7/soc.c
View File

@ -236,7 +236,7 @@ int arch_cpu_init(void)
init_csu();
/* Disable PDE bit of WMCR register */
imx_set_wdog_powerdown(false);
imx_wdog_disable_powerdown();
imx_enet_mdio_fixup();

40
board/dhelectronics/dh_imx6/dh_imx6_spl.c
View File

@ -140,40 +140,39 @@ static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
};
static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
.p0_mpwldectrl0 = 0x001F001F,
.p0_mpwldectrl1 = 0x001F001F,
.p1_mpwldectrl0 = 0x00440044,
.p1_mpwldectrl1 = 0x00440044,
.p0_mpdgctrl0 = 0x434B0350,
.p0_mpdgctrl1 = 0x034C0359,
.p1_mpdgctrl0 = 0x434B0350,
.p1_mpdgctrl1 = 0x03650348,
.p0_mprddlctl = 0x4436383B,
.p1_mprddlctl = 0x39393341,
.p0_mpwrdlctl = 0x35373933,
.p1_mpwrdlctl = 0x48254A36,
.p0_mpwldectrl0 = 0x0011000E,
.p0_mpwldectrl1 = 0x000E001B,
.p1_mpwldectrl0 = 0x00190015,
.p1_mpwldectrl1 = 0x00070018,
.p0_mpdgctrl0 = 0x42720306,
.p0_mpdgctrl1 = 0x026F0266,
.p1_mpdgctrl0 = 0x4273030A,
.p1_mpdgctrl1 = 0x02740240,
.p0_mprddlctl = 0x45393B3E,
.p1_mprddlctl = 0x403A3747,
.p0_mpwrdlctl = 0x40434541,
.p1_mpwrdlctl = 0x473E4A3B,
};
static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
.mem_speed = 1600,
.density = 4,
.density = 2,
.width = 64,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.trcd = 1312,
.trcmin = 5863,
.trasmin = 3750,
};
static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
.cs_density = 16,
.ncs = 1, /* single chip select */
.cs1_mirror = 0,
.cs1_mirror = 1,
.rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
.rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
@ -182,6 +181,8 @@ static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 3, /* 4 refresh commands per refresh cycle */
};
static void ccgr_init(void)
@ -388,7 +389,6 @@ void board_init_f(ulong dummy)
/* Perform DDR DRAM calibration */
udelay(100);
mmdc_do_write_level_calibration(&dhcom_ddr_info);
mmdc_do_dqs_calibration(&dhcom_ddr_info);
/* Clear the BSS. */

24
board/engicam/common/board.c
View File

@ -32,6 +32,30 @@ static void mmc_late_init(void)
}
#endif
static void setenv_fdt_file(void)
{
const char *cmp_dtb = CONFIG_DEFAULT_DEVICE_TREE;
if (!strcmp(cmp_dtb, "imx6q-icore")) {
if (is_mx6dq())
env_set("fdt_file", "imx6q-icore.dtb");
else if(is_mx6dl() || is_mx6solo())
env_set("fdt_file", "imx6dl-icore.dtb");
} else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) {
if (is_mx6dq())
env_set("fdt_file", "imx6q-icore-rqs.dtb");
else if(is_mx6dl() || is_mx6solo())
env_set("fdt_file", "imx6dl-icore-rqs.dtb");
} else if (!strcmp(cmp_dtb, "imx6ul-geam-kit"))
env_set("fdt_file", "imx6ul-geam-kit.dtb");
else if (!strcmp(cmp_dtb, "imx6ul-isiot-mmc"))
env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))
env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand"))
env_set("fdt_file", "imx6ul-isiot-nand.dtb");
}
int board_late_init(void)
{
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>

1
board/engicam/common/board.h
View File

@ -6,7 +6,6 @@
#ifndef _BOARD_H_
#define _BOARD_H_
void setenv_fdt_file(void);
void setup_gpmi_nand(void);
void setup_display(void);
#endif /* _BOARD_H_ */

42
board/engicam/common/spl.c
View File

@ -39,6 +39,48 @@ static iomux_v3_cfg_t const uart_pads[] = {
#endif
};
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
return 0;
else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
return 0;
else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
return 0;
else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
return 0;
else
return -1;
}
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
u32 bmode = imx6_src_get_boot_mode();
u8 boot_dev = BOOT_DEVICE_MMC1;
switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
/* SD/eSD - BOOT_DEVICE_MMC1 */
break;
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
/* MMC/eMMC */
boot_dev = BOOT_DEVICE_MMC2;
break;
default:
/* Default - BOOT_DEVICE_MMC1 */
printf("Wrong board boot order\n");
break;
}
spl_boot_list[0] = boot_dev;
}
#endif
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{

8
board/engicam/geam6ul/MAINTAINERS
View File

@ -1,8 +0,0 @@
GEAM6UL BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/engicam/geam6ul
F: include/configs/imx6-engicam.h
F: configs/imx6ul_geam_mmc_defconfig
F: configs/imx6ul_geam_nand_defconfig
F: arch/arm/dts/imx6ul-geam-kit.dts

28
board/engicam/geam6ul/README
View File

@ -1,28 +0,0 @@
How to use U-Boot on Engicam GEAM6UL Starter Kit:
-------------------------------------------------
- Configure U-Boot for Engicam GEAM6UL:
$ make mrproper
$ make imx6ul_geam_mmc_defconfig
$ make
This will generate the SPL image called SPL and the u-boot-dtb.img.
- Flash the SPL image into the micro SD card:
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
- Flash the u-boot-dtb.img image into the micro SD card:
sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
- Jumper settings:
MMC Boot: JM3 Closed
- Connect the Serial cable between the Starter Kit and the PC for the console.
(J28 is the Linux Serial console connector)
- Insert the micro SD card in the board, power it up and U-Boot messages should
come up.

12
board/engicam/icorem6_rqs/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_MX6Q_ICORE_RQS
config SYS_BOARD
default "icorem6_rqs"
config SYS_VENDOR
default "engicam"
config SYS_CONFIG_NAME
default "imx6-engicam"
endif

9
board/engicam/icorem6_rqs/MAINTAINERS
View File

@ -1,9 +0,0 @@
ICOREM6QDL_RQS BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/engicam/icorem6_rqs
F: include/configs/imx6-engicam.h
F: configs/imx6qdl_icore_rqs_defconfig
F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
F: arch/arm/dts/imx6q-icore-rqs.dts
F: arch/arm/dts/imx6dl-icore-rqs.dts

6
board/engicam/icorem6_rqs/Makefile
View File

@ -1,6 +0,0 @@
# Copyright (C) 2016 Amarula Solutions B.V.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := icorem6_rqs.o

124
board/engicam/icorem6_rqs/icorem6_rqs.c
View File

@ -6,129 +6,20 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
return devno;
return devno - 1;
}
#endif
void setenv_fdt_file(void)
{
if (is_mx6dq())
env_set("fdt_file", "imx6q-icore-rqs.dtb");
else if(is_mx6dl() || is_mx6solo())
env_set("fdt_file", "imx6dl-icore-rqs.dtb");
}
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR, 1, 4},
{USDHC4_BASE_ADDR, 1, 8},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC3_BASE_ADDR:
case USDHC4_BASE_ADDR:
ret = 1;
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC3
* mmc1 USDHC4
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 1:
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
@ -154,17 +45,4 @@ void board_boot_order(u32 *spl_boot_list)
spl_boot_list[0] = boot_dev;
}
#endif
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
return 0;
else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
return 0;
else
return -1;
}
#endif
#endif /* CONFIG_SPL_BUILD */

4
board/engicam/geam6ul/Kconfig → board/engicam/imx6q/Kconfig
View File

@ -1,7 +1,7 @@
if TARGET_MX6UL_GEAM
if TARGET_MX6Q_ENGICAM
config SYS_BOARD
default "geam6ul"
default "imx6q"
config SYS_VENDOR
default "engicam"

8
board/engicam/icorem6/MAINTAINERS → board/engicam/imx6q/MAINTAINERS
View File

@ -1,10 +1,14 @@
ICOREM6QDL BOARD
MX6Q_ENGICAM BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/engicam/icorem6
F: board/engicam/imx6q
F: include/configs/imx6-engicam.h
F: configs/imx6qdl_icore_mmc_defconfig
F: configs/imx6qdl_icore_nand_defconfig
F: configs/imx6qdl_icore_rqs_defconfig
F: arch/arm/dts/imx6qdl-icore.dtsi
F: arch/arm/dts/imx6q-icore.dts
F: arch/arm/dts/imx6dl-icore.dts
F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
F: arch/arm/dts/imx6q-icore-rqs.dts
F: arch/arm/dts/imx6dl-icore-rqs.dts

2
board/engicam/geam6ul/Makefile → board/engicam/imx6q/Makefile
View File

@ -3,4 +3,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := geam6ul.o
obj-y := imx6q.o

9
board/engicam/icorem6_rqs/README → board/engicam/imx6q/README
View File

@ -1,9 +1,12 @@
How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Kit:
----------------------------------------------------------------------------------
Hsow to use U-Boot on Engicam i.CoreM6 (RQS) Solo/DualLite/Quad/Dual Starter Kit:
--------------------------------------------------------------------------------
$ make mrproper
- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual/Solo/DualLite:
- Configure U-Boot for Engicam i.CoreM6 Quad/Duali/Solo/DualLite:
$ make imx6qdl_icore_mmc_defconfig
- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Duali/Solo/DualLite:
$ make imx6qdl_icore_rqs_defconfig
- Build U-Boot

98
board/engicam/icorem6/icorem6.c → board/engicam/imx6q/imx6q.c
View File

@ -7,7 +7,6 @@
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
@ -26,13 +25,12 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
iomux_v3_cfg_t gpmi_pads[] = {
static iomux_v3_cfg_t gpmi_pads[] = {
IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
@ -192,96 +190,10 @@ void setup_display(void)
}
#endif /* CONFIG_VIDEO_IPUV3 */
void setenv_fdt_file(void)
#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
if (is_mx6dq())
env_set("fdt_file", "imx6q-icore.dtb");
else if(is_mx6dl() || is_mx6solo())
env_set("fdt_file", "imx6dl-icore.dtb");
}
#ifdef CONFIG_SPL_BUILD
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC1_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC1
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
/* i.CoreM6 RQS has USDHC3 for SD and USDHC4 for eMMC */
return (devno == 0) ? 0: (devno - 1);
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
return 0;
else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
return 0;
else
return -1;
}
#endif
#endif /* CONFIG_SPL_BUILD */

4
board/engicam/icorem6/Kconfig → board/engicam/imx6ul/Kconfig
View File

@ -1,7 +1,7 @@
if TARGET_MX6Q_ICORE
if TARGET_MX6UL_ENGICAM
config SYS_BOARD
default "icorem6"
default "imx6ul"
config SYS_VENDOR
default "engicam"

9
board/engicam/isiotmx6ul/MAINTAINERS → board/engicam/imx6ul/MAINTAINERS
View File

@ -1,11 +1,14 @@
ISIOTMX6UL BOARD
MX6UL_ENGICAM BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/engicam/isiotmx6ul
F: board/engicam/imx6ul
F: include/configs/imx6-engicam.h
F: configs/imx6ul_isiot_mmc_defconfig
F: configs/imx6ul_geam_mmc_defconfig
F: configs/imx6ul_geam_nand_defconfig
F: configs/imx6ul_isiot_emmc_defconfig
F: configs/imx6ul_isiot_mmc_defconfig
F: configs/imx6ul_isiot_nand_defconfig
F: arch/arm/dts/imx6ul-geam-kit.dts
F: arch/arm/dts/imx6ul-isiot.dtsi
F: arch/arm/dts/imx6ul-isiot-mmc.dts
F: arch/arm/dts/imx6ul-isiot-emmc.dts

2
board/engicam/icorem6/Makefile → board/engicam/imx6ul/Makefile
View File

@ -3,4 +3,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := icorem6.o
obj-y := imx6ul.o

11
board/engicam/icorem6/README → board/engicam/imx6ul/README
View File

@ -1,10 +1,13 @@
How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:
-----------------------------------------------------------------------------
Hsow to use U-Boot on Engicam GEAM6UL and Is.IoT MX6UL Starter Kit:
-------------------------------------------------------------------
$ make mrproper
- Configure U-Boot for Engicam i.CoreM6 Quad/Dual/Solo/DualLite:
$ make imx6qdl_icore_mmc_defconfig
- Configure U-Boot for Engicam GEAM6UL:
$ make imx6ul_geam_mmc_defconfig
- Configure U-Boot for Engicam Is.IoT MX6UL:
$ make imx6ul_isiot_mmc_defconfig
- Build U-Boot
$ make

88
board/engicam/geam6ul/geam6ul.c → board/engicam/imx6ul/imx6ul.c
View File

@ -90,88 +90,10 @@ void setup_gpmi_nand(void)
}
#endif /* CONFIG_NAND_MXS */
void setenv_fdt_file(void)
#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
if (is_mx6ul())
env_set("fdt_file", "imx6ul-geam-kit.dtb");
/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
return (devno == 0) ? 0 : 1;
}
#ifdef CONFIG_SPL_BUILD
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* VSELECT */
IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* CD */
IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* RST_B */
IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC1_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC1
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
#endif /* CONFIG_FSL_ESDHC */
#endif /* CONFIG_SPL_BUILD */
#endif

12
board/engicam/isiotmx6ul/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_MX6UL_ISIOT
config SYS_BOARD
default "isiotmx6ul"
config SYS_VENDOR
default "engicam"
config SYS_CONFIG_NAME
default "imx6-engicam"
endif

6
board/engicam/isiotmx6ul/Makefile
View File

@ -1,6 +0,0 @@
# Copyright (C) 2016 Amarula Solutions B.V.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := isiotmx6ul.o

28
board/engicam/isiotmx6ul/README
View File

@ -1,28 +0,0 @@
How to use U-Boot on Engicam Is.IoT MX6UL Starter Kit:
-----------------------------------------------------
- Configure U-Boot for Engicam Is.IoT MX6UL
$ make mrproper
$ make imx6ul_isiot_mmc_defconfig
$ make
This will generate the SPL image called SPL and the u-boot-dtb.img.
- Flash the SPL image into the micro SD card:
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
- Flash the u-boot-dtb.img image into the micro SD card:
sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
- Jumper settings:
MMC Boot: JM3 Closed
- Connect the Serial cable between the Starter Kit and the PC for the console.
(J28 is the Linux Serial console connector)
- Insert the micro SD card in the board, power it up and U-Boot messages should
come up.

241
board/engicam/isiotmx6ul/isiotmx6ul.c
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@ -1,241 +0,0 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
static iomux_v3_cfg_t const nand_pads[] = {
IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
};
void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
SETUP_IOMUX_PADS(nand_pads);
clrbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
/*
* config gpmi and bch clock to 100 MHz
* bch/gpmi select PLL2 PFD2 400M
* 100M = 400M / 4
*/
clrbits_le32(&mxc_ccm->cscmr1,
MXC_CCM_CSCMR1_BCH_CLK_SEL |
MXC_CCM_CSCMR1_GPMI_CLK_SEL);
clrsetbits_le32(&mxc_ccm->cscdr1,
MXC_CCM_CSCDR1_BCH_PODF_MASK |
MXC_CCM_CSCDR1_GPMI_PODF_MASK,
(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif /* CONFIG_NAND_MXS */
#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
return (devno == 0) ? 0 : 1;
}
#endif
void setenv_fdt_file(void)
{
if (is_mx6ul()) {
#ifdef CONFIG_ENV_IS_IN_MMC
env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
#else
env_set("fdt_file", "imx6ul-isiot-nand.dtb");
#endif
}
}
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* VSELECT */
IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* CD */
IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* RST_B */
IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 4},
{USDHC2_BASE_ADDR, 0, 8},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
SETUP_IOMUX_PADS(usdhc2_pads);
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
u32 bmode = imx6_src_get_boot_mode();
u8 boot_dev = BOOT_DEVICE_MMC1;
switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
/* SD/eSD - BOOT_DEVICE_MMC1 */
break;
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
/* MMC/eMMC */
boot_dev = BOOT_DEVICE_MMC2;
break;
default:
/* Default - BOOT_DEVICE_MMC1 */
printf("Wrong board boot order\n");
break;
}
spl_boot_list[0] = boot_dev;
}
#endif
#endif /* CONFIG_FSL_ESDHC */
#endif /* CONFIG_SPL_BUILD */

2
board/ge/bx50v3/Makefile
View File

@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := bx50v3.o vpd_reader.o
obj-y := bx50v3.o

2
board/ge/bx50v3/bx50v3.c
View File

@ -28,7 +28,7 @@
#include <input.h>
#include <pwm.h>
#include <stdlib.h>
#include "vpd_reader.h"
#include "../common/vpd_reader.h"
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_I2C_EEPROM_ADDR

228
board/ge/bx50v3/vpd_reader.c
View File

@ -1,228 +0,0 @@
/*
* Copyright 2016 General Electric Company
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "vpd_reader.h"
#include <linux/bch.h>
#include <stdlib.h>
/* BCH configuration */
const struct {
int header_ecc_capability_bits;
int data_ecc_capability_bits;
unsigned int prim_poly;
struct {
int min;
int max;
} galois_field_order;
} bch_configuration = {
.header_ecc_capability_bits = 4,
.data_ecc_capability_bits = 16,
.prim_poly = 0,
.galois_field_order = {
.min = 5,
.max = 15,
},
};
static int calculate_galois_field_order(size_t source_length)
{
int gfo = bch_configuration.galois_field_order.min;
for (; gfo < bch_configuration.galois_field_order.max &&
((((1 << gfo) - 1) - ((int)source_length * 8)) < 0);
gfo++) {
}
if (gfo == bch_configuration.galois_field_order.max) {
return -1;
}
return gfo + 1;
}
static int verify_bch(int ecc_bits, unsigned int prim_poly,
uint8_t * data, size_t data_length,
const uint8_t * ecc, size_t ecc_length)
{
int gfo = calculate_galois_field_order(data_length);
if (gfo < 0) {
return -1;
}
struct bch_control * bch = init_bch(gfo, ecc_bits, prim_poly);
if (!bch) {
return -1;
}
if (bch->ecc_bytes != ecc_length) {
free_bch(bch);
return -1;
}
unsigned * errloc = (unsigned *)calloc(data_length, sizeof(unsigned));
int errors = decode_bch(
bch, data, data_length, ecc, NULL, NULL, errloc);
free_bch(bch);
if (errors < 0) {
free(errloc);
return -1;
}
if (errors > 0) {
for (int n = 0; n < errors; n++) {
if (errloc[n] >= 8 * data_length) {
/* n-th error located in ecc (no need for data correction) */
} else {
/* n-th error located in data */
data[errloc[n] / 8] ^= 1 << (errloc[n] % 8);
}
}
}
free(errloc);
return 0;
}
static const int ID = 0;
static const int LEN = 1;
static const int VER = 2;
static const int TYP = 3;
static const int BLOCK_SIZE = 4;
static const uint8_t HEADER_BLOCK_ID = 0x00;
static const uint8_t HEADER_BLOCK_LEN = 18;
static const uint32_t HEADER_BLOCK_MAGIC = 0xca53ca53;
static const size_t HEADER_BLOCK_VERIFY_LEN = 14;
static const size_t HEADER_BLOCK_ECC_OFF = 14;
static const size_t HEADER_BLOCK_ECC_LEN = 4;
static const uint8_t ECC_BLOCK_ID = 0xFF;
int vpd_reader(
size_t size,
uint8_t * data,
void * userdata,
int (*fn)(
void * userdata,
uint8_t id,
uint8_t version,
uint8_t type,
size_t size,
uint8_t const * data))
{
if ( size < HEADER_BLOCK_LEN
|| data == NULL
|| fn == NULL) {
return -EINVAL;
}
/*
* +--------------------+--------------------+--//--+--------------------+
* | header block | data block | ... | ecc block |
* +--------------------+--------------------+--//--+--------------------+
* : : :
* +------+-------+-----+ +------+-------------+
* | id | magic | ecc | | ... | ecc |
* | len | off | | +------+-------------+
* | ver | size | | :
* | type | | | :
* +------+-------+-----+ :
* : : : :
* <----- [1] ----> <----------- [2] ----------->
*
* Repair (if necessary) the contents of header block [1] by using a
* 4 byte ECC located at the end of the header block. A successful
* return value means that we can trust the header.
*/
int ret = verify_bch(
bch_configuration.header_ecc_capability_bits,
bch_configuration.prim_poly,
data,
HEADER_BLOCK_VERIFY_LEN,
&data[HEADER_BLOCK_ECC_OFF],
HEADER_BLOCK_ECC_LEN);
if (ret < 0) {
return ret;
}
/* Validate header block { id, length, version, type }. */
if ( data[ID] != HEADER_BLOCK_ID
|| data[LEN] != HEADER_BLOCK_LEN
|| data[VER] != 0
|| data[TYP] != 0
|| ntohl(*(uint32_t *)(&data[4])) != HEADER_BLOCK_MAGIC) {
return -EINVAL;
}
uint32_t offset = ntohl(*(uint32_t *)(&data[8]));
uint16_t size_bits = ntohs(*(uint16_t *)(&data[12]));
/* Check that ECC header fits. */
if (offset + 3 >= size) {
return -EINVAL;
}
/* Validate ECC block. */
uint8_t * ecc = &data[offset];
if ( ecc[ID] != ECC_BLOCK_ID
|| ecc[LEN] < BLOCK_SIZE
|| ecc[LEN] + offset > size
|| ecc[LEN] - BLOCK_SIZE != size_bits / 8
|| ecc[VER] != 1
|| ecc[TYP] != 1) {
return -EINVAL;
}
/*
* Use the header block to locate the ECC block and verify the data
* blocks [2] against the ecc block ECC.
*/
ret = verify_bch(
bch_configuration.data_ecc_capability_bits,
bch_configuration.prim_poly,
&data[data[LEN]],
offset - data[LEN],
&data[offset + BLOCK_SIZE],
ecc[LEN] - BLOCK_SIZE);
if (ret < 0) {
return ret;
}
/* Stop after ECC. Ignore possible zero padding. */
size = offset;
for (;;) {
/* Move to next block. */
size -= data[LEN];
data += data[LEN];
if (size == 0) {
/* Finished iterating through blocks. */
return 0;
}
if ( size < BLOCK_SIZE
|| data[LEN] < BLOCK_SIZE) {
/* Not enough data for a header, or short header. */
return -EINVAL;
}
ret = fn(
userdata,
data[ID],
data[VER],
data[TYP],
data[LEN] - BLOCK_SIZE,
&data[BLOCK_SIZE]);
if (ret) {
return ret;
}
}
}

7
board/ge/common/Makefile Normal file
View File

@ -0,0 +1,7 @@
#
# Copyright 2017 General Electric Company
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := vpd_reader.o

197
board/ge/common/vpd_reader.c Normal file
View File

@ -0,0 +1,197 @@
/*
* Copyright 2016 General Electric Company
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "vpd_reader.h"
#include <linux/bch.h>
#include <stdlib.h>
/* BCH configuration */
const struct {
int header_ecc_capability_bits;
int data_ecc_capability_bits;
unsigned int prim_poly;
struct {
int min;
int max;
} galois_field_order;
} bch_configuration = {
.header_ecc_capability_bits = 4,
.data_ecc_capability_bits = 16,
.prim_poly = 0,
.galois_field_order = {
.min = 5,
.max = 15,
},
};
static int calculate_galois_field_order(size_t source_length)
{
int gfo = bch_configuration.galois_field_order.min;
for (; gfo < bch_configuration.galois_field_order.max &&
((((1 << gfo) - 1) - ((int)source_length * 8)) < 0);
gfo++) {
}
if (gfo == bch_configuration.galois_field_order.max)
return -1;
return gfo + 1;
}
static int verify_bch(int ecc_bits, unsigned int prim_poly, u8 *data,
size_t data_length, const u8 *ecc, size_t ecc_length)
{
int gfo = calculate_galois_field_order(data_length);
if (gfo < 0)
return -1;
struct bch_control *bch = init_bch(gfo, ecc_bits, prim_poly);
if (!bch)
return -1;
if (bch->ecc_bytes != ecc_length) {
free_bch(bch);
return -1;
}
unsigned int *errloc = (unsigned int *)calloc(data_length,
sizeof(unsigned int));
int errors = decode_bch(bch, data, data_length, ecc, NULL, NULL,
errloc);
free_bch(bch);
if (errors < 0) {
free(errloc);
return -1;
}
if (errors > 0) {
for (int n = 0; n < errors; n++) {
if (errloc[n] >= 8 * data_length) {
/*
* n-th error located in ecc (no need for data
* correction)
*/
} else {
/* n-th error located in data */
data[errloc[n] / 8] ^= 1 << (errloc[n] % 8);
}
}
}
free(errloc);
return 0;
}
static const int ID;
static const int LEN = 1;
static const int VER = 2;
static const int TYP = 3;
static const int BLOCK_SIZE = 4;
static const u8 HEADER_BLOCK_ID;
static const u8 HEADER_BLOCK_LEN = 18;
static const u32 HEADER_BLOCK_MAGIC = 0xca53ca53;
static const size_t HEADER_BLOCK_VERIFY_LEN = 14;
static const size_t HEADER_BLOCK_ECC_OFF = 14;
static const size_t HEADER_BLOCK_ECC_LEN = 4;
static const u8 ECC_BLOCK_ID = 0xFF;
int vpd_reader(size_t size, u8 *data, void *userdata,
int (*fn)(void *userdata, u8 id, u8 version, u8 type,
size_t size, u8 const *data))
{
if (size < HEADER_BLOCK_LEN || !data || !fn)
return -EINVAL;
/*
* +--------------------+----------------+--//--+--------------------+
* | header block | data block | ... | ecc block |
* +--------------------+----------------+--//--+--------------------+
* : : :
* +------+-------+-----+ +------+-------------+
* | id | magic | ecc | | ... | ecc |
* | len | off | | +------+-------------+
* | ver | size | | :
* | type | | | :
* +------+-------+-----+ :
* : : : :
* <----- [1] ----> <--------- [2] --------->
*
* Repair (if necessary) the contents of header block [1] by using a
* 4 byte ECC located at the end of the header block. A successful
* return value means that we can trust the header.
*/
int ret = verify_bch(bch_configuration.header_ecc_capability_bits,
bch_configuration.prim_poly, data,
HEADER_BLOCK_VERIFY_LEN,
&data[HEADER_BLOCK_ECC_OFF], HEADER_BLOCK_ECC_LEN);
if (ret < 0)
return ret;
/* Validate header block { id, length, version, type }. */
if (data[ID] != HEADER_BLOCK_ID || data[LEN] != HEADER_BLOCK_LEN ||
data[VER] != 0 || data[TYP] != 0 ||
ntohl(*(u32 *)(&data[4])) != HEADER_BLOCK_MAGIC)
return -EINVAL;
u32 offset = ntohl(*(u32 *)(&data[8]));
u16 size_bits = ntohs(*(u16 *)(&data[12]));
/* Check that ECC header fits. */
if (offset + 3 >= size)
return -EINVAL;
/* Validate ECC block. */
u8 *ecc = &data[offset];
if (ecc[ID] != ECC_BLOCK_ID || ecc[LEN] < BLOCK_SIZE ||
ecc[LEN] + offset > size ||
ecc[LEN] - BLOCK_SIZE != size_bits / 8 || ecc[VER] != 1 ||
ecc[TYP] != 1)
return -EINVAL;
/*
* Use the header block to locate the ECC block and verify the data
* blocks [2] against the ecc block ECC.
*/
ret = verify_bch(bch_configuration.data_ecc_capability_bits,
bch_configuration.prim_poly, &data[data[LEN]],
offset - data[LEN], &data[offset + BLOCK_SIZE],
ecc[LEN] - BLOCK_SIZE);
if (ret < 0)
return ret;
/* Stop after ECC. Ignore possible zero padding. */
size = offset;
for (;;) {
/* Move to next block. */
size -= data[LEN];
data += data[LEN];
if (size == 0) {
/* Finished iterating through blocks. */
return 0;
}
if (size < BLOCK_SIZE || data[LEN] < BLOCK_SIZE) {
/* Not enough data for a header, or short header. */
return -EINVAL;
}
ret = fn(userdata, data[ID], data[VER], data[TYP],
data[LEN] - BLOCK_SIZE, &data[BLOCK_SIZE]);
if (ret)
return ret;
}
}

14
board/ge/bx50v3/vpd_reader.h → board/ge/common/vpd_reader.h
View File

@ -12,14 +12,6 @@
*
* Returns Non-zero on error. Negative numbers encode errno.
*/
int vpd_reader(
size_t size,
uint8_t * data,
void * userdata,
int (*fn)(
void * userdata,
uint8_t id,
uint8_t version,
uint8_t type,
size_t size,
uint8_t const * data));
int vpd_reader(size_t size, u8 *data, void *userdata,
int (*fn)(void *userdata, u8 id, u8 version, u8 type,
size_t size, u8 const *data));

17
board/ge/mx53ppd/Kconfig Normal file
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@ -0,0 +1,17 @@
# SPDX-License-Identifier: GPL-2.0+
if TARGET_MX53PPD
config SYS_BOARD
default "mx53ppd"
config SYS_VENDOR
default "ge"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "mx53ppd"
endif

7
board/ge/mx53ppd/MAINTAINERS Normal file
View File

@ -0,0 +1,7 @@
MX53PPD BOARD
M: Antti Mäentausta <antti.maentausta@ge.com>
M: Martyn Welch <martyn.welch@collabora.co.uk>
S: Maintained
F: board/freescale/mx53ppd/
F: include/configs/mx53ppd.h
F: configs/mx53ppd_defconfig

12
board/ge/mx53ppd/Makefile Normal file
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@ -0,0 +1,12 @@
# Copyright 2017 General Electric Company
#
# Based on board/freescale/mx53loco/Makefile:
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
# Jason Liu <r64343@freescale.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += mx53ppd.o
obj-$(CONFIG_VIDEO) += mx53ppd_video.o

87
board/ge/mx53ppd/imximage.cfg Normal file
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@ -0,0 +1,87 @@
/*
* Copyright 2017 General Electric Company
*
* Based on board/freescale/mx53loco/imximage.cfg:
*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x53fa8004 0x00194005
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
DATA 4 0x53fa8564 0x00300040
DATA 4 0x53fa8568 0x00300040
DATA 4 0x53fa8570 0x00300000
DATA 4 0x53fa8574 0x00300000
DATA 4 0x53fa8578 0x00300000
DATA 4 0x53fa857c 0x00300040
DATA 4 0x53fa8580 0x00300040
DATA 4 0x53fa8584 0x00300000
DATA 4 0x53fa8588 0x00300000
DATA 4 0x53fa8590 0x00300040
DATA 4 0x53fa8594 0x00300000
DATA 4 0x53fa86f0 0x00300000
DATA 4 0x53fa86f4 0x00000000
DATA 4 0x53fa86fc 0x00000000
DATA 4 0x53fa8714 0x00000000
DATA 4 0x53fa8718 0x00300000
DATA 4 0x53fa871c 0x00300000
DATA 4 0x53fa8720 0x00300000
DATA 4 0x53fa8728 0x00300000
DATA 4 0x53fa872c 0x00300000
DATA 4 0x63fd9088 0x35343535
DATA 4 0x63fd9090 0x4d444c44
DATA 4 0x63fd907c 0x01370138
DATA 4 0x63fd9080 0x013b013c
DATA 4 0x63fd9018 0x00111740
DATA 4 0x63fd9000 0x85190000
DATA 4 0x63fd900c 0x8b8f52e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
DATA 4 0x63fd902c 0x000026d2
DATA 4 0x63fd9030 0x008f0e21
DATA 4 0x63fd9008 0x09333030
DATA 4 0x63fd9004 0x0002002d
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00468031
DATA 4 0x63fd901c 0x052080b0
DATA 4 0x63fd901c 0x04008040
DATA 4 0x63fd901c 0x0000803a
DATA 4 0x63fd901c 0x0000803b
DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x05208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00005800
DATA 4 0x63fd9040 0x05380003
DATA 4 0x63fd9058 0x00011110
DATA 4 0x63fd901c 0x00000000

457
board/ge/mx53ppd/mx53ppd.c Normal file
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@ -0,0 +1,457 @@
/*
* Copyright 2017 General Electric Company
*
* Based on board/freescale/mx53loco/mx53loco.c:
*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
#include <linux/errno.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/mx5_video.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/gpio.h>
#include <power/pmic.h>
#include <dialog_pmic.h>
#include <fsl_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <watchdog.h>
#include "ppd_gpio.h"
#include <stdlib.h>
#include "../../ge/common/vpd_reader.h"
#include <rtc.h>
#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
DECLARE_GLOBAL_DATA_PTR;
/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */
#define VPD_EEPROM_BUS 2
/* Address of 24C08 EEPROM. */
#define VPD_EEPROM_ADDR 0x50
#define VPD_EEPROM_ADDR_LEN 1
static u32 mx53_dram_size[2];
phys_size_t get_effective_memsize(void)
{
/*
* WARNING: We must override get_effective_memsize() function here
* to report only the size of the first DRAM bank. This is to make
* U-Boot relocator place U-Boot into valid memory, that is, at the
* end of the first DRAM bank. If we did not override this function
* like so, U-Boot would be placed at the address of the first DRAM
* bank + total DRAM size - sizeof(uboot), which in the setup where
* each DRAM bank contains 512MiB of DRAM would result in placing
* U-Boot into invalid memory area close to the end of the first
* DRAM bank.
*/
return mx53_dram_size[0];
}
int dram_init(void)
{
mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = mx53_dram_size[1];
return 0;
}
u32 get_board_rev(void)
{
return get_cpu_rev() & ~(0xF << 8);
}
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
/* request VBUS power enable pin, GPIO7_8 */
imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
return 0;
}
#endif
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
PAD_CTL_ODE),
NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
PAD_CTL_HYS | PAD_CTL_PKE),
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC3_BASE_ADDR},
{MMC_SDHC1_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
return 1;
}
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_DSE_HIGH)
int board_mmc_init(bd_t *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
MX53_PAD_EIM_DA11__GPIO3_11,
};
static const iomux_v3_cfg_t sd2_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
MX53_PAD_EIM_DA13__GPIO3_13,
};
u32 index;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
imx_iomux_v3_setup_multiple_pads(sd1_pads,
ARRAY_SIZE(sd1_pads));
break;
case 1:
imx_iomux_v3_setup_multiple_pads(sd2_pads,
ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return 0;
}
#endif
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
static void setup_iomux_i2c(void)
{
static const iomux_v3_cfg_t i2c1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
}
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
.gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
.gp = IMX_GPIO_NR(3, 28)
},
.sda = {
.i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
.gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
.gp = IMX_GPIO_NR(3, 21)
}
};
static int clock_1GHz(void)
{
int ret;
u32 ref_clk = MXC_HCLK;
/*
* After increasing voltage to 1.25V, we can switch
* CPU clock to 1GHz and DDR to 400MHz safely
*/
ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
if (ret) {
printf("CPU: Switch CPU clock to 1GHZ failed\n");
return -1;
}
ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
if (ret) {
printf("CPU: Switch DDR clock to 400MHz failed\n");
return -1;
}
return 0;
}
void ppd_gpio_init(void)
{
int i;
imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
}
int board_early_init_f(void)
{
setup_iomux_fec();
setup_iomux_lcd();
ppd_gpio_init();
return 0;
}
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
#define VPD_TYPE_INVALID 0x00
#define VPD_BLOCK_NETWORK 0x20
#define VPD_BLOCK_HWID 0x44
#define VPD_PRODUCT_PPD 4
#define VPD_HAS_MAC1 0x1
#define VPD_MAC_ADDRESS_LENGTH 6
struct vpd_cache {
u8 product_id;
u8 has;
unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
};
/*
* Extracts MAC and product information from the VPD.
*/
static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size,
u8 const *data)
{
struct vpd_cache *vpd = (struct vpd_cache *)userdata;
if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
size >= 1) {
vpd->product_id = data[0];
} else if (id == VPD_BLOCK_NETWORK && version == 1 &&
type != VPD_TYPE_INVALID) {
if (size >= 6) {
vpd->has |= VPD_HAS_MAC1;
memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
}
}
return 0;
}
static void process_vpd(struct vpd_cache *vpd)
{
int fec_index = -1;
if (vpd->product_id == VPD_PRODUCT_PPD)
fec_index = 0;
if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
eth_env_set_enetaddr("ethaddr", vpd->mac1);
}
static int read_vpd(uint eeprom_bus)
{
struct vpd_cache vpd;
int res;
int size = 1024;
u8 *data;
unsigned int current_i2c_bus = i2c_get_bus_num();
res = i2c_set_bus_num(eeprom_bus);
if (res < 0)
return res;
data = malloc(size);
if (!data)
return -ENOMEM;
res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size);
if (res == 0) {
memset(&vpd, 0, sizeof(vpd));
vpd_reader(size, data, &vpd, vpd_callback);
process_vpd(&vpd);
}
free(data);
i2c_set_bus_num(current_i2c_bus);
return res;
}
static void check_time(void)
{
int ret, i;
struct rtc_time tm;
u8 retry = 3;
unsigned int current_i2c_bus = i2c_get_bus_num();
ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
if (ret < 0)
return;
rtc_init();
for (i = 0; i < retry; i++) {
ret = rtc_get(&tm);
if (!ret || ret == -EINVAL)
break;
}
if (ret < 0)
env_set("rtc_status", "RTC_ERROR");
if (tm.tm_year > 2037) {
tm.tm_sec = 0;
tm.tm_min = 0;
tm.tm_hour = 0;
tm.tm_mday = 1;
tm.tm_wday = 2;
tm.tm_mon = 1;
tm.tm_year = 2036;
for (i = 0; i < retry; i++) {
ret = rtc_set(&tm);
if (!ret)
break;
}
if (ret < 0)
env_set("rtc_status", "RTC_ERROR");
}
i2c_set_bus_num(current_i2c_bus);
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
mxc_set_sata_internal_clock();
setup_iomux_i2c();
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
return 0;
}
int misc_init_r(void)
{
const char *cause;
/* We care about WDOG only, treating everything else as
* a power-on-reset.
*/
if (get_imx_reset_cause() & 0x0010)
cause = "WDOG";
else
cause = "POR";
env_set("bootcause", cause);
return 0;
}
int board_late_init(void)
{
int res;
read_vpd(VPD_EEPROM_BUS);
res = clock_1GHz();
if (res != 0)
return res;
print_cpuinfo();
hw_watchdog_init();
check_time();
return 0;
}
int checkboard(void)
{
puts("Board: GE PPD\n");
return 0;
}

135
board/ge/mx53ppd/mx53ppd_video.c Normal file
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/*
* Copyright 2017 General Electric Company
*
* Based on board/freescale/mx53loco/mx53loco_video.c:
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Fabio Estevam <fabio.estevam@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/list.h>
#include <asm/gpio.h>
#include <asm/arch/iomux-mx53.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <pwm.h>
#include "ppd_gpio.h"
#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
static struct fb_videomode const nv_spwg = {
.name = "NV-SPWGRGB888",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 15384,
.left_margin = 16,
.right_margin = 210,
.upper_margin = 10,
.lower_margin = 22,
.hsync_len = 30,
.vsync_len = 13,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
};
void setup_iomux_lcd(void)
{
static const iomux_v3_cfg_t lcd_pads[] = {
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
};
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
}
static void lcd_enable(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* Set LDB_DI0 as clock source for IPU_DI0 */
clrsetbits_le32(&mxc_ccm->cscmr2,
MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK,
MXC_CCM_CSCMR2_DI0_CLK_SEL(
MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK));
/* Turn on IPU LDB DI0 clocks */
setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3));
/* Turn on IPU DI0 clocks */
setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3));
/* Configure LDB */
writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
&iomux->gpr[2]);
/* Enable backlights */
pwm_init(1, 0, 0);
/* duty cycle 5000000ns, period: 5000000ns */
pwm_config(1, 5000000, 5000000);
/* Backlight Power */
gpio_direction_output(BACKLIGHT_ENABLE, 1);
pwm_enable(1);
}
static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
lcd_enable();
return 0;
}
U_BOOT_CMD(
ppd_lcd_enable, 1, 1, do_lcd_enable,
"enable PPD LCD",
"no parameters"
);
int board_video_skip(void)
{
int ret;
ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24);
if (ret)
printf("Display cannot be configured: %d\n", ret);
return ret;
}

96
board/ge/mx53ppd/ppd_gpio.h Normal file
View File

@ -0,0 +1,96 @@
/*
* (C) Copyright 2015 General Electric Company
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PPD_GPIO_H_
#define __PPD_GPIO_H_
#include <asm/arch/iomux-mx53.h>
#include <asm/gpio.h>
#define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
static const iomux_v3_cfg_t ppd_pads[] = {
/* FEC */
MX53_PAD_EIM_A22__GPIO2_16,
/* UART */
NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL),
/* Video */
MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */
MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */
MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */
MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */
MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */
MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */
MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */
/* I2C */
MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */
/* SPI */
MX53_PAD_DISP0_DAT23__GPIO5_17,
MX53_PAD_KEY_COL2__GPIO4_10,
MX53_PAD_KEY_ROW2__GPIO4_11,
MX53_PAD_KEY_COL3__GPIO4_12,
};
struct gpio_cfg {
unsigned int gpio;
int value;
};
#define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16)
#define UD_SCAN_CTRL IMX_GPIO_NR(5, 21)
#define LR_SCAN_CTRL IMX_GPIO_NR(5, 20)
#define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3)
#define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2)
#define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18)
#define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28)
#define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28)
#define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29)
#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
#define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29)
#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
#define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
#define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
#define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
#define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
static const struct gpio_cfg ppd_gpios[] = {
/* FEC */
/* Drive Low as GPIO output for 25ms per Eth Phy IX spec */
/* Then Drive High as GPIO output to bring Eth Phy IC out of reset */
{ RESET_IMX535_ETHERNET_PHY_N, 0 },
{ RESET_IMX535_ETHERNET_PHY_N, 1 },
/* Video */
{ UD_SCAN_CTRL, 0 },
{ LR_SCAN_CTRL, 1 },
#ifdef PROPRIETARY_CHANGES
{ LVDS0_MUX_CTRL, 1 },
#else
{ LVDS0_MUX_CTRL, 0 },
#endif
{ LVDS1_MUX_CTRL, 1 },
{ HOST_CONTROLLED_RESET_TO_LCD_N, 1 },
{ DATA_WIDTH_CTRL, 0 },
{ RESET_DP0_TRANSMITTER_N, 1 },
{ RESET_DP1_TRANSMITTER_N, 1 },
{ POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
{ POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
{ ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
{ BACKLIGHT_ENABLE, 0 },
{ RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
{ ECSPI1_CS0, 1 },
{ ECSPI1_CS1, 1 },
{ ECSPI1_CS2, 1 },
{ ECSPI1_CS3, 1 },
};
#endif /* __PPD_GPIO_H_ */

2
board/wandboard/spl.c
View File

@ -399,6 +399,8 @@ static void spl_dram_init(void)
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
}
udelay(100);
}
void board_init_f(ulong dummy)

2
configs/cgtqmx6eval_defconfig
View File

@ -10,7 +10,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

2
configs/cm_fx6_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
CONFIG_AHCI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80

2
configs/dh_imx6_defconfig
View File

@ -10,7 +10,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL=y

2
configs/gwventana_emmc_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set

2
configs/gwventana_gw5904_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set

2
configs/gwventana_nand_defconfig
View File

@ -15,7 +15,7 @@ CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set

3
configs/imx6qdl_icore_mmc_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@ -48,3 +48,4 @@ CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000

2
configs/imx6qdl_icore_nand_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set

4
configs/imx6qdl_icore_rqs_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE_RQS=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
CONFIG_CRC32_VERIFY=y
@ -40,3 +41,4 @@ CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_SYS_MALLOC_F_LEN=0x2000

3
configs/imx6ul_geam_mmc_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_GEAM=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@ -40,3 +40,4 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_SYS_MALLOC_F_LEN=0x2000

2
configs/imx6ul_geam_nand_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_GEAM=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set

3
configs/imx6ul_isiot_emmc_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_ISIOT=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@ -38,3 +38,4 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_SYS_MALLOC_F_LEN=0x2000

3
configs/imx6ul_isiot_mmc_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_ISIOT=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@ -40,3 +40,4 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_SYS_MALLOC_F_LEN=0x2000

2
configs/imx6ul_isiot_nand_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_ISIOT=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set

2
configs/mccmon6_nor_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MCCMON6=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y

2
configs/mccmon6_sd_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_TARGET_MCCMON6=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y

39
configs/mx53ppd_defconfig Normal file
View File

@ -0,0 +1,39 @@
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_MX53PPD=y
CONFIG_FIT=y
CONFIG_BOOTCOUNT=y
CONFIG_BOOTCOUNT_EXT=y
CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE="mmc"
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
CONFIG_SYS_BOOTCOUNT_EXT_NAME="/boot/failures"
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
CONFIG_NETDEVICES=y
CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_I2C=y
CONFIG_RTC_S35392A=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
CONFIG_MMC=y

2
configs/mx6cuboxi_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y

2
configs/mx6sabreauto_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

2
configs/mx6sabresd_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

1
configs/mx6sxsabresd_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set

2
configs/pfla02_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y

2
configs/pico-imx6ul_defconfig
View File

@ -12,7 +12,9 @@ CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y

2
configs/udoo_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y

1
configs/wandboard_defconfig
View File

@ -11,7 +11,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y

2
drivers/Kconfig
View File

@ -10,6 +10,8 @@ source "drivers/ata/Kconfig"
source "drivers/block/Kconfig"
source "drivers/bootcount/Kconfig"
source "drivers/clk/Kconfig"
source "drivers/cpu/Kconfig"

58
drivers/bootcount/Kconfig Normal file
View File

@ -0,0 +1,58 @@
#
# Boot count configuration
#
menu "Boot count support"
config BOOTCOUNT
bool "Enable Boot count support"
help
Enable boot count support, which provides the ability to store the
number of times the board has booted on a number of different
persistent storage mediums.
if BOOTCOUNT
config BOOTCOUNT_EXT
bool "Boot counter on EXT filesystem"
help
Add support for maintaining boot count in a file on an EXT
filesystem.
if BOOTCOUNT_EXT
config SYS_BOOTCOUNT_EXT_INTERFACE
string "Interface on which to find boot counter EXT filesystem"
default "mmc"
depends on BOOTCOUNT_EXT
help
Set the interface to use when locating the filesystem to use for the
boot counter.
config SYS_BOOTCOUNT_EXT_DEVPART
string "Partition of the boot counter EXT filesystem"
default "0:1"
depends on BOOTCOUNT_EXT
help
Set the partition to use when locating the filesystem to use for the
boot counter.
config SYS_BOOTCOUNT_EXT_NAME
string "Path and filename of the EXT filesystem based boot counter"
default "/boot/failures"
depends on BOOTCOUNT_EXT
help
Set the filename and path of the file used to store the boot counter.
config SYS_BOOTCOUNT_ADDR
hex "RAM address used for reading and writing the boot counter"
default 0x7000A000
depends on BOOTCOUNT_EXT
help
Set the address used for reading and writing the boot counter.
endif
endif
endmenu

1
drivers/bootcount/Makefile
View File

@ -9,3 +9,4 @@ obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o
obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o
obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o
obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o

62
drivers/bootcount/bootcount_ext.c Normal file
View File

@ -0,0 +1,62 @@
/*
* Copyright (c) 2017 General Electric Company. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <bootcount.h>
#include <fs.h>
#include <mapmem.h>
#define BC_MAGIC 0xbc
void bootcount_store(ulong a)
{
u8 *buf;
loff_t len;
int ret;
if (fs_set_blk_dev(CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE,
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART, FS_TYPE_EXT)) {
puts("Error selecting device\n");
return;
}
buf = map_sysmem(CONFIG_SYS_BOOTCOUNT_ADDR, 2);
buf[0] = BC_MAGIC;
buf[1] = (a & 0xff);
unmap_sysmem(buf);
ret = fs_write(CONFIG_SYS_BOOTCOUNT_EXT_NAME,
CONFIG_SYS_BOOTCOUNT_ADDR, 0, 2, &len);
if (ret != 0)
puts("Error storing bootcount\n");
}
ulong bootcount_load(void)
{
u8 *buf;
loff_t len_read;
int ret;
if (fs_set_blk_dev(CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE,
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART, FS_TYPE_EXT)) {
puts("Error selecting device\n");
return 0;
}
ret = fs_read(CONFIG_SYS_BOOTCOUNT_EXT_NAME, CONFIG_SYS_BOOTCOUNT_ADDR,
0, 2, &len_read);
if (ret != 0 || len_read != 2) {
puts("Error loading bootcount\n");
return 0;
}
buf = map_sysmem(CONFIG_SYS_BOOTCOUNT_ADDR, 2);
if (buf[0] == BC_MAGIC)
ret = buf[1];
unmap_sysmem(buf);
return ret;
}

25
drivers/i2c/mxc_i2c.c
View File

@ -317,16 +317,19 @@ static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
temp |= I2CR_MTX | I2CR_TX_NO_AK;
writeb(temp, base + (I2CR << reg_shift));
/* write slave address */
ret = tx_byte(i2c_bus, chip << 1);
if (ret < 0)
return ret;
while (alen--) {
ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
if (alen >= 0) {
/* write slave address */
ret = tx_byte(i2c_bus, chip << 1);
if (ret < 0)
return ret;
while (alen--) {
ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
if (ret < 0)
return ret;
}
}
return 0;
}
@ -537,9 +540,11 @@ static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
if (ret < 0)
return ret;
temp = readb(base + (I2CR << reg_shift));
temp |= I2CR_RSTA;
writeb(temp, base + (I2CR << reg_shift));
if (alen >= 0) {
temp = readb(base + (I2CR << reg_shift));
temp |= I2CR_RSTA;
writeb(temp, base + (I2CR << reg_shift));
}
ret = tx_byte(i2c_bus, (chip << 1) | 1);
if (ret < 0) {

7
drivers/pinctrl/nxp/pinctrl-imx6.c
View File

@ -13,6 +13,11 @@
static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info;
/* FIXME Before reloaction, BSS is overlapped with DT area */
static struct imx_pinctrl_soc_info imx6ul_pinctrl_soc_info = {
.flags = ZERO_OFFSET_VALID,
};
static struct imx_pinctrl_soc_info imx6_snvs_pinctrl_soc_info = {
.flags = ZERO_OFFSET_VALID,
};
@ -32,7 +37,7 @@ static const struct udevice_id imx6_pinctrl_match[] = {
{ .compatible = "fsl,imx6sll-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info },
{ .compatible = "fsl,imx6sll-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6ul_pinctrl_soc_info },
{ .compatible = "fsl,imx6ull-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info },
{ /* sentinel */ }
};

2
drivers/pwm/pwm-imx-util.c
View File

@ -23,10 +23,12 @@ struct pwm_regs *pwm_id_to_reg(int pwm_id)
return (struct pwm_regs *)PWM1_BASE_ADDR;
case 1:
return (struct pwm_regs *)PWM2_BASE_ADDR;
#ifdef CONFIG_MX6
case 2:
return (struct pwm_regs *)PWM3_BASE_ADDR;
case 3:
return (struct pwm_regs *)PWM4_BASE_ADDR;
#endif
#ifdef CONFIG_MX6SX
case 4:
return (struct pwm_regs *)PWM5_BASE_ADDR;

6
drivers/rtc/Kconfig
View File

@ -30,4 +30,10 @@ config RTC_DS1307
Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and
compatible Real Time Clock devices.
config RTC_S35392A
bool "Enable S35392A driver"
select BITREVERSE
help
Enable s35392a driver which provides rtc get and set function.
endmenu

1
drivers/rtc/Makefile
View File

@ -49,5 +49,6 @@ obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
obj-$(CONFIG_RTC_RV3029) += rv3029.o
obj-$(CONFIG_RTC_RX8025) += rx8025.o
obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
obj-$(CONFIG_RTC_S35392A) += s35392a.o
obj-$(CONFIG_SANDBOX) += sandbox_rtc.o
obj-$(CONFIG_RTC_X1205) += x1205.o

365
drivers/rtc/s35392a.c Normal file
View File

@ -0,0 +1,365 @@
/*
* SII Semiconductor Corporation S35392A RTC driver.
*
* Copyright (c) 2017, General Electric Company
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <command.h>
#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <linux/bitrev.h>
#include <rtc.h>
#define S35390A_CMD_STATUS1 0x30
#define S35390A_CMD_STATUS2 0x31
#define S35390A_CMD_TIME1 0x32
#define S35390A_CMD_TIME2 0x33
#define S35390A_CMD_INT2_REG1 0x35
#define S35390A_BYTE_YEAR 0
#define S35390A_BYTE_MONTH 1
#define S35390A_BYTE_DAY 2
#define S35390A_BYTE_WDAY 3
#define S35390A_BYTE_HOURS 4
#define S35390A_BYTE_MINS 5
#define S35390A_BYTE_SECS 6
/* flags for STATUS1 */
#define S35390A_FLAG_POC 0x01
#define S35390A_FLAG_BLD 0x02
#define S35390A_FLAG_INT2 0x04
#define S35390A_FLAG_24H 0x40
#define S35390A_FLAG_RESET 0x80
/*
* If either BLD or POC is set, then the chip has lost power long enough for
* the time value to become invalid.
*/
#define S35390A_LOW_VOLTAGE (S35390A_FLAG_POC | S35390A_FLAG_BLD)
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
#ifdef DEBUG_RTC
#define DEBUGR(fmt, args...) printf(fmt, ##args)
#else
#define DEBUGR(fmt, args...)
#endif
/*---------------------------------------------------------------------*/
#ifdef CONFIG_DM_RTC
#define DEV_TYPE struct udevice
#else
/* Local udevice */
struct ludevice {
u8 chip;
};
#define DEV_TYPE struct ludevice
struct ludevice dev;
#endif
#define msleep(a) udelay(a * 1000)
int lowvoltage;
static int s35392a_rtc_reset(DEV_TYPE *dev);
static int s35392a_rtc_read(DEV_TYPE *dev, u8 reg, u8 *buf, int len)
{
int ret;
#ifdef CONFIG_DM_RTC
/* TODO: we need to tweak the chip address to reg */
ret = dm_i2c_read(dev, 0, buf, len);
#else
(void)dev;
ret = i2c_read(reg, 0, -1, buf, len);
#endif
return ret;
}
static int s35392a_rtc_write(DEV_TYPE *dev, u8 reg, u8 *buf, int len)
{
int ret;
#ifdef CONFIG_DM_RTC
/* TODO: we need to tweak the chip address to reg */
ret = dm_i2c_write(dev, 0, buf, 1);
#else
(void)dev;
ret = i2c_write(reg, 0, 0, buf, len);
#endif
return ret;
}
static int s35392a_rtc_read8(DEV_TYPE *dev, unsigned int reg)
{
u8 val;
int ret;
ret = s35392a_rtc_read(dev, reg, &val, sizeof(val));
return ret < 0 ? ret : val;
}
static int s35392a_rtc_write8(DEV_TYPE *dev, unsigned int reg, int val)
{
int ret;
u8 lval = val;
ret = s35392a_rtc_write(dev, reg, &lval, sizeof(lval));
return ret < 0 ? ret : 0;
}
static int validate_time(const struct rtc_time *tm)
{
if ((tm->tm_year < 2000) || (tm->tm_year > 2099))
return -EINVAL;
if ((tm->tm_mon < 1) || (tm->tm_mon > 12))
return -EINVAL;
if ((tm->tm_mday < 1) || (tm->tm_mday > 31))
return -EINVAL;
if ((tm->tm_wday < 0) || (tm->tm_wday > 6))
return -EINVAL;
if ((tm->tm_hour < 0) || (tm->tm_hour > 23))
return -EINVAL;
if ((tm->tm_min < 0) || (tm->tm_min > 59))
return -EINVAL;
if ((tm->tm_sec < 0) || (tm->tm_sec > 59))
return -EINVAL;
return 0;
}
void s35392a_rtc_init(DEV_TYPE *dev)
{
int status;
status = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1);
if (status < 0)
goto error;
DEBUGR("init: S35390A_CMD_STATUS1: 0x%x\n", status);
lowvoltage = status & S35390A_LOW_VOLTAGE ? 1 : 0;
if (status & S35390A_FLAG_POC)
/*
* Do not communicate for 0.5 seconds since the power-on
* detection circuit is in operation.
*/
msleep(500);
else if (!lowvoltage)
/*
* If both POC and BLD are unset everything is fine.
*/
return;
if (lowvoltage)
printf("RTC low voltage detected\n");
if (!s35392a_rtc_reset(dev))
return;
error:
printf("Error RTC init.\n");
}
/* Get the current time from the RTC */
static int s35392a_rtc_get(DEV_TYPE *dev, struct rtc_time *tm)
{
u8 date[7];
int ret, i;
if (lowvoltage) {
DEBUGR("RTC low voltage detected\n");
return -EINVAL;
}
ret = s35392a_rtc_read(dev, S35390A_CMD_TIME1, date, sizeof(date));
if (ret < 0) {
DEBUGR("Error reading date from RTC\n");
return -EIO;
}
/* This chip returns the bits of each byte in reverse order */
for (i = 0; i < 7; ++i)
date[i] = bitrev8(date[i]);
tm->tm_sec = bcd2bin(date[S35390A_BYTE_SECS]);
tm->tm_min = bcd2bin(date[S35390A_BYTE_MINS]);
tm->tm_hour = bcd2bin(date[S35390A_BYTE_HOURS] & ~S35390A_FLAG_24H);
tm->tm_wday = bcd2bin(date[S35390A_BYTE_WDAY]);
tm->tm_mday = bcd2bin(date[S35390A_BYTE_DAY]);
tm->tm_mon = bcd2bin(date[S35390A_BYTE_MONTH]);
tm->tm_year = bcd2bin(date[S35390A_BYTE_YEAR]) + 2000;
DEBUGR("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
return 0;
}
/* Set the RTC */
static int s35392a_rtc_set(DEV_TYPE *dev, const struct rtc_time *tm)
{
int i, ret;
int status;
u8 date[7];
DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
ret = validate_time(tm);
if (ret < 0)
return -EINVAL;
/* We support only 24h mode */
ret = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1);
if (ret < 0)
return -EIO;
status = ret;
ret = s35392a_rtc_write8(dev, S35390A_CMD_STATUS1,
status | S35390A_FLAG_24H);
if (ret < 0)
return -EIO;
date[S35390A_BYTE_YEAR] = bin2bcd(tm->tm_year - 2000);
date[S35390A_BYTE_MONTH] = bin2bcd(tm->tm_mon);
date[S35390A_BYTE_DAY] = bin2bcd(tm->tm_mday);
date[S35390A_BYTE_WDAY] = bin2bcd(tm->tm_wday);
date[S35390A_BYTE_HOURS] = bin2bcd(tm->tm_hour);
date[S35390A_BYTE_MINS] = bin2bcd(tm->tm_min);
date[S35390A_BYTE_SECS] = bin2bcd(tm->tm_sec);
/* This chip expects the bits of each byte to be in reverse order */
for (i = 0; i < 7; ++i)
date[i] = bitrev8(date[i]);
ret = s35392a_rtc_write(dev, S35390A_CMD_TIME1, date, sizeof(date));
if (ret < 0) {
DEBUGR("Error writing date to RTC\n");
return -EIO;
}
/* Now we have time. Reset the low voltage status */
lowvoltage = 0;
return 0;
}
/* Reset the RTC. */
static int s35392a_rtc_reset(DEV_TYPE *dev)
{
int buf;
int ret;
unsigned int initcount = 0;
buf = S35390A_FLAG_RESET;
initialize:
ret = s35392a_rtc_write8(dev, S35390A_CMD_STATUS1, buf);
if (ret < 0)
return -EIO;
ret = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1);
if (ret < 0)
return -EIO;
buf = ret;
if (!lowvoltage)
lowvoltage = buf & S35390A_LOW_VOLTAGE ? 1 : 0;
if (buf & S35390A_LOW_VOLTAGE) {
/* Try up to five times to reset the chip */
if (initcount < 5) {
++initcount;
goto initialize;
} else {
return -EIO;
}
}
return 0;
}
#ifndef CONFIG_DM_RTC
int rtc_get(struct rtc_time *tm)
{
return s35392a_rtc_get(&dev, tm);
}
int rtc_set(struct rtc_time *tm)
{
return s35392a_rtc_set(&dev, tm);
}
void rtc_reset(void)
{
s35392a_rtc_reset(&dev);
}
void rtc_init(void)
{
s35392a_rtc_init(&dev);
}
#else
static int s35392a_probe(struct udevice *dev)
{
s35392a_rtc_init(dev);
return 0;
}
static const struct rtc_ops s35392a_rtc_ops = {
.get = s35392a_rtc_get,
.set = s35392a_rtc_set,
.read8 = s35392a_rtc_read8,
.write8 = s35392a_rtc_write8,
.reset = s35392a_rtc_reset,
};
static const struct udevice_id s35392a_rtc_ids[] = {
{ .compatible = "sii,s35392a-rtc" },
{ }
};
U_BOOT_DRIVER(s35392a_rtc) = {
.name = "s35392a_rtc",
.id = UCLASS_RTC,
.probe = s35392a_probe,
.of_match = s35392a_rtc_ids,
.ops = &s35392a_rtc_ops,
};
#endif

10
fs/ext4/ext4_common.c
View File

@ -660,6 +660,11 @@ static int search_dir(struct ext2_inode *parent_inode, char *dirname)
offset = 0;
do {
if (offset & 3) {
printf("Badly aligned ext2_dirent\n");
break;
}
dir = (struct ext2_dirent *)(block_buffer + offset);
direntname = (char*)(dir) + sizeof(struct ext2_dirent);
@ -880,6 +885,11 @@ static int unlink_filename(char *filename, unsigned int blknr)
offset = 0;
do {
if (offset & 3) {
printf("Badly aligned ext2_dirent\n");
break;
}
previous_dir = dir;
dir = (struct ext2_dirent *)(block_buffer + offset);
direntname = (char *)(dir) + sizeof(struct ext2_dirent);

10
fs/ext4/ext4fs.c
View File

@ -64,6 +64,9 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
char *delayed_buf = NULL;
short status;
if (blocksize <= 0)
return -1;
/* Adjust len so it we can't read past the end of the file. */
if (len + pos > filesize)
len = (filesize - pos);
@ -127,6 +130,7 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
(blockend >> log2blksz);
}
} else {
int n;
if (previous_block_number != -1) {
/* spill */
status = ext4fs_devread(delayed_start,
@ -137,7 +141,11 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
return -1;
previous_block_number = -1;
}
memset(buf, 0, blocksize - skipfirst);
/* Zero no more than `len' bytes. */
n = blocksize - skipfirst;
if (n > len)
n = len;
memset(buf, 0, n);
}
buf += blocksize - skipfirst;
}

11
include/configs/imx6-engicam.h
View File

@ -215,17 +215,6 @@
# endif
# include "imx6_spl.h"
# ifdef CONFIG_SPL_BUILD
# if defined(CONFIG_TARGET_MX6Q_ICORE_RQS) || defined(CONFIG_TARGET_MX6UL_ISIOT)
# define CONFIG_SYS_FSL_USDHC_NUM 2
# else
# define CONFIG_SYS_FSL_USDHC_NUM 1
# endif
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
# undef CONFIG_DM_GPIO
# undef CONFIG_DM_MMC
# endif
#endif
#endif /* __IMX6_ENGICAM_CONFIG_H */

248
include/configs/mx53ppd.h Normal file
View File

@ -0,0 +1,248 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* Configuration settings for Freescale MX53 low cost board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
#define CONSOLE_DEV "ttymxc0"
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
#define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */
/* Eth Configs */
#define CONFIG_MII
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
#define CONFIG_USB_EHCI_MX5
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_SYS_RTC_BUS_NUM 2
#define CONFIG_SYS_I2C_RTC_ADDR 0x30
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Command definition */
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
#define PPD_CONFIG_NFS \
"nfsserver=192.168.252.95\0" \
"gatewayip=192.168.252.95\0" \
"netmask=255.255.255.0\0" \
"ipaddr=192.168.252.99\0" \
"kernsize=0x2000\0" \
"use_dhcp=0\0" \
"nfsroot=/opt/springdale/rd\0" \
"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
"${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
"choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \
"set getcmd dhcp; else set kern_ipconf " \
"ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \
"set getcmd tftp; fi\0" \
"nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \
"${nfsserver}:${image}; bootm ${loadaddr}\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
PPD_CONFIG_NFS \
"bootlimit=10\0" \
"image=/boot/fitImage\0" \
"fdt_high=0xffffffff\0" \
"dev=mmc\0" \
"devnum=0\0" \
"rootdev=mmcblk0p\0" \
"quiet=quiet loglevel=0\0" \
"console=" CONSOLE_DEV "\0" \
"lvds=ldb\0" \
"setargs=setenv bootargs ${lvds} jtag=on mem=2G " \
"vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \
"console=${console} ${rtc_status}\0" \
"bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
"rootwait ${bootargs}\0" \
"doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
"then setenv quiet; fi\0" \
"hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
"/boot/bootcause/firstboot\0" \
"swappartitions=setexpr partnum 3 - ${partnum}\0" \
"failbootcmd=" \
"ppd_lcd_enable; " \
"msg=\"Monitor failed to start. " \
"Try again, or contact GE Service for support.\"; " \
"echo $msg; " \
"setenv stdout vga; " \
"echo \"\n\n\n\n \" $msg; " \
"setenv stdout serial; " \
"mw.b 0x7000A000 0xbc; " \
"mw.b 0x7000A001 0x00; " \
"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
"altbootcmd=" \
"run doquiet; " \
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
"run hasfirstboot || setenv partnum 0; " \
"if test ${partnum} != 0; then " \
"setenv bootcause REVERT; " \
"run swappartitions loadimage doboot; " \
"fi; " \
"run failbootcmd\0" \
"loadimage=" \
"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
"doboot=" \
"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
"run setargs; " \
"run bootargs_emmc; " \
"bootm ${loadaddr}\0" \
"tryboot=" \
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
"run loadimage || run swappartitions && run loadimage || " \
"setenv partnum 0 && echo MISSING IMAGE;" \
"run doboot; " \
"run failbootcmd\0" \
"video-mode=" \
"lcd:800x480-24@60,monitor=lcd\0" \
#define CONFIG_MMCBOOTCOMMAND \
"if mmc dev ${devnum}; then " \
"run doquiet; " \
"run tryboot; " \
"fi; " \
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 48 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x70000000
#define CONFIG_SYS_MEMTEST_END 0x70010000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_CMD_FUSE
#define CONFIG_FSL_IIM
#define CONFIG_SYS_I2C_SPEED 100000
/* I2C1 */
#define CONFIG_SYS_NUM_I2C_BUSES 9
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
}
#define CONFIG_BCH
#define CONFIG_BOOTCOUNT_LIMIT
/* Backlight Control */
#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66666000
/* Framebuffer and LCD */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#endif
#endif /* __CONFIG_H */

5
include/configs/mx6sxsabresd.h
View File

@ -57,9 +57,9 @@
"videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
"mmcdev=2\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"finduuid=part uuid mmc 2:2 uuid\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
@ -67,6 +67,7 @@
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run finduuid; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \

23
include/configs/pico-imx6ul.h
View File

@ -47,6 +47,13 @@
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=uboot raw 0x2 0x400 mmcpart 1;" \
"boot part 0 1;" \
"/zImage ext4 0 1;" \
"/imx6ul-pico-hobbit.dtb ext4 0 1;" \
"rootfs part 0 2\0" \
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_EXTRA_ENV_SETTINGS \
@ -58,14 +65,19 @@
"fdt_addr=0x83000000\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
CONFIG_DFU_ENV_SETTINGS \
"finduuid=part uuid mmc 0:2 uuid\0" \
"partitions=" \
"uuid_disk=${uuid_gpt_disk};" \
"name=boot,size=16MiB;name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
"setup_emmc=gpt write mmc 0 $partitions; reset;\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run finduuid; " \
"run mmcargs; " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
@ -144,6 +156,5 @@
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#endif /* __PICO_IMX6UL_CONFIG_H */

3
lib/Kconfig
View File

@ -80,6 +80,9 @@ config TPL_TINY_MEMSET
config RBTREE
bool
config BITREVERSE
bool "Bit reverse library from Linux"
source lib/dhry/Kconfig
menu "Security support"