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imx: clock support enet2 anatop clock support

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To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
   To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Peng Fan 2015-08-12 17:46:50 +08:00 committed by Stefano Babic
parent fc684e87a1
commit 6d97dc10a8
9 changed files with 31 additions and 12 deletions
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23
arch/arm/cpu/armv7/mx6/clock.c
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@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num)
#endif
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(enum enet_freq freq)
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq)
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
reg = readl(&anatop->pll_enet);
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
reg |= freq;
if (fec_id == 0) {
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
} else if (fec_id == 1) {
/* Only i.MX6SX/UL support ENET2 */
if (!(is_cpu_type(MXC_CPU_MX6SX) ||
is_cpu_type(MXC_CPU_MX6UL)))
return -EINVAL;
reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
} else {
return -EINVAL;
}
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq)
}
/* Enable FEC clock */
reg |= BM_ANADIG_PLL_ENET_ENABLE;
if (fec_id == 0)
reg |= BM_ANADIG_PLL_ENET_ENABLE;
else
reg |= BM_ANADIG_PLL_ENET2_ENABLE;
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
writel(reg, &anatop->pll_enet);

2
arch/arm/include/asm/arch-mx6/clock.h
View File

@ -64,7 +64,7 @@ int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);

6
arch/arm/include/asm/arch-mx6/crm_regs.h
View File

@ -1052,6 +1052,12 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
/* ENET2 for i.MX6SX/UL */
#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
(((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
#define BP_ANADIG_PFD_480_PFD3_FRAC 24

2
board/aristainetos/aristainetos-v1.c
View File

@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis)
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
ret = enable_fec_anatop_clock(ENET_50MHZ);
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
if (ret)
return ret;

2
board/barco/platinum/platinum_picon.c
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@ -148,7 +148,7 @@ int platinum_setup_enet(void)
/* set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
return enable_fec_anatop_clock(ENET_50MHZ);
return enable_fec_anatop_clock(0, ENET_50MHZ);
}
int platinum_setup_i2c(void)

2
board/freescale/mx6qsabreauto/mx6qsabreauto.c
View File

@ -361,7 +361,7 @@ static void setup_fec(void)
* select ENET MAC0 TX clock from PLL
*/
imx_iomux_set_gpr_register(5, 9, 1, 1);
enable_fec_anatop_clock(ENET_125MHZ);
enable_fec_anatop_clock(0, ENET_125MHZ);
}
setup_iomux_enet();

2
board/freescale/mx6slevk/mx6slevk.c
View File

@ -279,7 +279,7 @@ static int setup_fec(void)
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
return enable_fec_anatop_clock(ENET_50MHZ);
return enable_fec_anatop_clock(0, ENET_50MHZ);
}
#endif

2
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View File

@ -170,7 +170,7 @@ static int setup_fec(void)
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
return enable_fec_anatop_clock(ENET_125MHZ);
return enable_fec_anatop_clock(0, ENET_125MHZ);
}
int board_eth_init(bd_t *bis)

2
board/solidrun/mx6cuboxi/mx6cuboxi.c
View File

@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis)
struct mii_dev *bus;
struct phy_device *phydev;
int ret = enable_fec_anatop_clock(ENET_25MHZ);
int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
if (ret)
return ret;