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armv7/fsl-ls102xa: Workaround for DDR erratum A008514

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This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Yao Yuan 2015-12-05 14:59:13 +08:00 committed by York Sun
parent 0b8bc6314e
commit 6c4a1eba3f
2 changed files with 11 additions and 1 deletions
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10
arch/arm/cpu/armv7/ls102xa/soc.c
View File

@ -76,5 +76,15 @@ int arch_soc_init(void)
SCFG_SNPCNFGCR_DBG_RD_WR |
SCFG_SNPCNFGCR_EDMA_SNP);
/*
* Memory controller require a register write before being enabled.
* Affects: DDR
* Register: EDDRTQCFG
* Description: Memory controller performance is not optimal with
* default internal target queue register values.
* Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
*/
out_be32(&scfg->eddrtqcfg, 0x63b20042);
return 0;
}

2
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View File

@ -230,7 +230,7 @@ struct ccsr_scfg {
u32 scfgrevcr;
u32 coresrencr;
u32 pex2pmrdsr;
u32 ddrc1cr;
u32 eddrtqcfg;
u32 ddrc2cr;
u32 ddrc3cr;
u32 ddrc4cr;