leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

x86: broadwell: Move init of debug UART to cpu.c

Browse Source 
At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2019-04-25 21:58:50 -06:00 committed by Bin Meng
parent 4eabf1e54b
commit 6b83b29578
2 changed files with 13 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/x86/cpu/broadwell/cpu.c
View File

@ -12,7 +12,9 @@
#include <asm/cpu_x86.h>
#include <asm/cpu_common.h>
#include <asm/intel_regs.h>
#include <asm/lpc_common.h>
#include <asm/msr.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/turbo.h>
#include <asm/arch/cpu.h>
@ -156,6 +158,17 @@ int print_cpuinfo(void)
return 0;
}
void board_debug_uart_init(void)
{
struct udevice *bus = NULL;
/* com1 / com2 decode range */
pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
PCI_SIZE_16);
}
/*
* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly

11
arch/x86/cpu/broadwell/sdram.c
View File

@ -194,17 +194,6 @@ int misc_init_r(void)
return 0;
}
void board_debug_uart_init(void)
{
struct udevice *bus = NULL;
/* com1 / com2 decode range */
pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
PCI_SIZE_16);
}
static const struct udevice_id broadwell_syscon_ids[] = {
{ .compatible = "intel,me", .data = X86_SYSCON_ME },
{ }