Xilinx changes for v2021.10

clk: - Add driver for Xilinx Clocking Wizard IP fdt: - Also record architecture in /fit-images net: - Fix plat/priv data handling in axi emac - Add support for 10G/25G speeds pca953x: - Add missing dependency on i2c serial: - Fix dependencies for DEBUG uart for pl010/pl011 - Add setconfig option for cadence serial driver watchdog: - Add cadence wdt expire now function zynq: - Update DT bindings to reflect the latest state and descriptions zynqmp: - Update DT bindings to reflect the latest state and descriptions - SPL: Add support for ECC DRAM initialization - Fix R5 core 1 handling logic - Enable firmware driver for mini configurations - Enable secure boot, regulators, wdt - Add support xck devices and 67dr - Add psu init for sm/smk-k26 SOMs - Add handling for MMC seq number via mmc_get_env_dev() - Handle reserved memory locations - Add support for u-boot.itb generation for secure OS - Handle BL32 handoffs for secure OS - Add support for 64bit addresses for u-boot.its generation - Change eeprom handling via nvmem aliases -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYN105QAKCRDKSWXLKUoM IZiFAJ9CIiEpHiBbnAhA0VOMGoaXHGULywCdED/5dNgVtc1C7y4avzETbEyWzD4= =CdMa -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.10 clk: - Add driver for Xilinx Clocking Wizard IP fdt: - Also record architecture in /fit-images net: - Fix plat/priv data handling in axi emac - Add support for 10G/25G speeds pca953x: - Add missing dependency on i2c serial: - Fix dependencies for DEBUG uart for pl010/pl011 - Add setconfig option for cadence serial driver watchdog: - Add cadence wdt expire now function zynq: - Update DT bindings to reflect the latest state and descriptions zynqmp: - Update DT bindings to reflect the latest state and descriptions - SPL: Add support for ECC DRAM initialization - Fix R5 core 1 handling logic - Enable firmware driver for mini configurations - Enable secure boot, regulators, wdt - Add support xck devices and 67dr - Add psu init for sm/smk-k26 SOMs - Add handling for MMC seq number via mmc_get_env_dev() - Handle reserved memory locations - Add support for u-boot.itb generation for secure OS - Handle BL32 handoffs for secure OS - Add support for 64bit addresses for u-boot.its generation - Change eeprom handling via nvmem aliases
2021-07-01 08:57:23 -04:00 · 2021-07-01 08:57:23 -04:00 · 6b69f15fd6
commit 6b69f15fd6
parent 90c2fd2af8 45576273e9
66 changed files with 2324 additions and 947 deletions
--- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
+++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
@ -15,10 +15,10 @@
 		     "xlnx,zynqmp";
 	chosen {
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = &eeprom;
 	};
 	aliases {
 		ethernet0 = &gem3;
+		nvmem0 = &eeprom;
 		serial0 = &uart0;
 	};
 };
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@ -95,7 +95,7 @@
 		};
 	};

-	amba: amba {
+	amba: axi {
 		u-boot,dm-pre-reloc;
 		compatible = "simple-bus";
 		#address-cells = <1>;
--- a/arch/arm/dts/zynq-syzygy-hub.dts
+++ b/arch/arm/dts/zynq-syzygy-hub.dts
@ -16,6 +16,7 @@
 		ethernet0 = &gem0;
 		serial0 = &uart0;
 		mmc0 = &sdhci0;
+		nvmem0 = &eeprom;
 		i2c0 = &i2c1;
 	};

@ -27,7 +28,6 @@
 	chosen {
 		bootargs = "";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = &eeprom;
 	};

 	usb_phy0: phy0 {
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@ -68,6 +68,12 @@
 	ocm: sram@fffc0000 {
 		compatible = "mmio-sram";
 		reg = <0xfffc0000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xfffc0000 0x10000>;
+		ocm-sram@0 {
+			reg = <0x0 0x10000>;
+		};
 	};
 };

--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@ -68,13 +68,12 @@
 	num-cs = <4>;
 	is-decoded-cs = <0>;
 	eeprom: eeprom@2 {
-		at25,byte-len = <8192>;
-		at25,addr-mode = <2>;
-		at25,page-size = <32>;
-
 		compatible = "atmel,at25";
 		reg = <2>;
 		spi-max-frequency = <1000000>;
+		size = <8192>;
+		address-width = <16>;
+		pagesize = <32>;
 	};
 };

--- a/arch/arm/dts/zynqmp-a2197-revA.dts
+++ b/arch/arm/dts/zynqmp-a2197-revA.dts
@ -18,13 +18,14 @@

 	aliases {
 		i2c0 = &i2c0;
+		nvmem0 = &eeprom1;
+		nvmem1 = &eeprom0;
 		serial0 = &uart0;
 	};

 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;
 	};

 	memory@0 {
@ -35,7 +36,6 @@

 &uart0 { /* uart0 MIO38-39 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &i2c0 {
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@ -2,7 +2,7 @@
 /*
 * Clock specification for Xilinx ZynqMP
 *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -67,13 +67,6 @@
 		#clock-cells = <0>;
 		clock-frequency = <27000000>;
 	};
-
-	dp_aclk: dp_aclk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-		clock-accuracy = <100>;
-	};
 };

 &zynqmp_firmware {
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@ -20,10 +20,10 @@

 	aliases {
 		ethernet0 = &gem0;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &dcc;
@ -32,7 +32,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = <&eeprom>;
 	};

 	memory@0 {
@ -124,7 +123,6 @@

 &uart0 { /* uart0 MIO38-39 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &sdhci1 { /* sd1 MIO45-51 cd in place */
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@ -19,9 +19,9 @@

 	aliases {
 		ethernet0 = &gem0;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		mmc0 = &sdhci0;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &dcc;
@ -31,7 +31,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = <&eeprom>;
 	};

 	memory@0 {
@ -75,7 +74,6 @@

 &uart0 { /* uart0 MIO38-39 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &gem0 { /* eth MDIO 76/77 */
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@ -19,11 +19,11 @@

 	aliases {
 		ethernet0 = &gem0;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -36,7 +36,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = <&eeprom>;
 	};

 	memory@0 {
@ -94,12 +93,10 @@

 &uart0 { /* uart0 MIO38-39 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &uart1 { /* uart1 MIO40-41 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &sdhci1 { /* sd1 MIO45-51 cd in place */
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@ -19,11 +19,11 @@

 	aliases {
 		ethernet0 = &gem0;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -36,7 +36,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = <&eeprom>;
 	};

 	memory@0 {
@ -90,12 +89,10 @@

 &uart0 { /* uart0 MIO38-39 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &uart1 { /* uart1 MIO40-41 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &sdhci1 { /* sd1 MIO45-51 cd in place */
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@ -19,11 +19,11 @@

 	aliases {
 		ethernet0 = &gem0;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -36,7 +36,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = <&eeprom>;
 	};

 	memory@0 {
@ -90,12 +89,10 @@

 &uart0 { /* uart0 MIO38-39 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &uart1 { /* uart1 MIO40-41 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &sdhci1 { /* sd1 MIO45-51 cd in place */
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@ -20,11 +20,11 @@

 	aliases {
 		ethernet0 = &gem0;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -36,8 +36,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = <&eeprom>;
-		/* xlnx,fmc-eeprom = FIXME */
 	};

 	memory@0 {
@ -68,12 +66,10 @@

 &uart0 { /* uart0 MIO38-39 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &uart1 { /* uart1 MIO40-41 */
 	status = "okay";
-	u-boot,dm-pre-reloc;
 };

 &sdhci1 { /* sd1 MIO45-51 cd in place */
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for KV260 revA Carrier Card
 *
- * (C) Copyright 2020, Xilinx, Inc.
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
 * SD level shifter:
 * "A" – A01 board un-modified (NXP)
@ -20,354 +20,316 @@
 /dts-v1/;
 /plugin/;

-/{
+&{/} {
 	compatible = "xlnx,zynqmp-sk-kv260-revA",
 		     "xlnx,zynqmp-sk-kv260-revY",
 		     "xlnx,zynqmp-sk-kv260-revZ",
 		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+};

-	fragment1 {
-		target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
+&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_default>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;

-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default", "gpio";
-			pinctrl-0 = <&pinctrl_i2c1_default>;
-			pinctrl-1 = <&pinctrl_i2c1_gpio>;
-			scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
-			sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+	u14: ina260@40 { /* u14 */
+		compatible = "ti,ina260";
+		#io-channel-cells = <1>;
+		label = "ina260-u14";
+		reg = <0x40>;
+	};
+	/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+};

-			u14: ina260@40 { /* u14 */
-				compatible = "ti,ina260";
-				#io-channel-cells = <1>;
-				label = "ina260-u14";
-				reg = <0x40>;
-			};
-			/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
-		};
+&amba {
+	ina260-u14 {
+		compatible = "iio-hwmon";
+		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
 	};

-	fragment1a {
-		target = <&amba>;
-		__overlay__ {
-			ina260-u14 {
-				compatible = "iio-hwmon";
-				io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
-			};
-
-			si5332_0: si5332_0 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <125000000>;
-			};
-
-			si5332_1: si5332_1 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <25000000>;
-			};
-
-			si5332_2: si5332_2 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <48000000>;
-			};
-
-			si5332_3: si5332_3 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <24000000>;
-			};
-
-			si5332_4: si5332_4 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <26000000>;
-			};
-
-			si5332_5: si5332_5 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <27000000>;
-			};
-		};
+	si5332_0: si5332_0 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
 	};

+	si5332_1: si5332_1 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	si5332_2: si5332_2 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <48000000>;
+	};
+
+	si5332_3: si5332_3 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
+
+	si5332_4: si5332_4 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+	};
+
+	si5332_5: si5332_5 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+};
+
 /* DP/USB 3.0 and SATA */
-	fragment2 {
-		target = <&psgtr>;
-		__overlay__ {
-			status = "okay";
-			/* pcie, usb3, sata */
-			clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
-			clock-names = "ref0", "ref1", "ref2";
-		};
+&psgtr {
+	status = "okay";
+	/* pcie, usb3, sata */
+	clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+	clock-names = "ref0", "ref1", "ref2";
+};
+
+&sata {
+	status = "okay";
+	/* SATA OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
+};
+
+&zynqmp_dpsub {
+	status = "disabled";
+	phy-names = "dp-phy0", "dp-phy1";
+	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+};
+
+&zynqmp_dpdma {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0_default>;
+	usbhub: usb5744 { /* u43 */
+		compatible = "microchip,usb5744";
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
 	};
+};

-	fragment3 {
-		target = <&sata>;
-		__overlay__ {
-			status = "okay";
-			/* SATA OOB timing settings */
-			ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
-			ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
-			ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
-			ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
-			ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
-			ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
-			ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
-			ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
-			phy-names = "sata-phy";
-			phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
-		};
-	};
+&dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+	snps,usb3_lpm_capable;
+	phy-names = "usb3-phy";
+	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+	maximum-speed = "super-speed";
+};

-	fragment4 {
-		target = <&zynqmp_dpsub>;
-		__overlay__ {
-			status = "disabled";
-			phy-names = "dp-phy0", "dp-phy1";
-			phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
-		};
-	};
+&sdhci1 { /* on CC with tuned parameters */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci1_default>;
+	/*
+	 * SD 3.0 requires level shifter and this property
+	 * should be removed if the board has level shifter and
+	 * need to work in UHS mode
+	 */
+	no-1-8-v;
+	disable-wp;
+	xlnx,mio-bank = <1>;
+};

-	fragment9 {
-		target = <&zynqmp_dpdma>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
+&gem3 { /* required by spec */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gem3_default>;
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";

-	fragment10 {
-		target = <&usb0>;
-		__overlay__ {
-			status = "okay";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb0_default>;
-			usbhub: usb5744 { /* u43 */
-				compatible = "microchip,usb5744";
-				reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
-			};
-		};
-	};
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <2>;

-	fragment11 {
-		target = <&dwc3_0>;
-		__overlay__ {
-			status = "okay";
-			dr_mode = "host";
-			snps,usb3_lpm_capable;
-			phy-names = "usb3-phy";
-			phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
-			maximum-speed = "super-speed";
-		};
-	};
-
-	fragment12 {
-		target = <&sdhci1>; /* on CC with tuned parameters */
-		__overlay__ {
-			status = "okay";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_sdhci1_default>;
-			/*
-			 * SD 3.0 requires level shifter and this property
-			 * should be removed if the board has level shifter and
-			 * need to work in UHS mode
-			 */
-			no-1-8-v;
-			disable-wp;
-			xlnx,mio-bank = <1>;
-		};
-	};
-
-	fragment13 {
-		target = <&gem3>; /* required by spec */
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "okay";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_gem3_default>;
-			phy-handle = <&phy0>;
-			phy-mode = "rgmii-id";
-
-			mdio: mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
-				reset-delay-us = <2>;
-
-				phy0: ethernet-phy@1 {
-					#phy-cells = <1>;
-					reg = <1>;
-					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
-					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
-					ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-					ti,dp83867-rxctrl-strap-quirk;
-				};
-			};
-		};
-	};
-
-	fragment14 {
-		target = <&pinctrl0>; /* required by spec */
-		__overlay__ {
-			status = "okay";
-
-			pinctrl_uart1_default: uart1-default {
-				conf {
-					groups = "uart1_9_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-					drive-strength = <12>;
-				};
-
-				conf-rx {
-					pins = "MIO37";
-					bias-high-impedance;
-				};
-
-				conf-tx {
-					pins = "MIO36";
-					bias-disable;
-				};
-
-				mux {
-					groups = "uart1_9_grp";
-					function = "uart1";
-				};
-			};
-
-			pinctrl_i2c1_default: i2c1-default {
-				conf {
-					groups = "i2c1_6_grp";
-					bias-pull-up;
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				mux {
-					groups = "i2c1_6_grp";
-					function = "i2c1";
-				};
-			};
-
-			pinctrl_i2c1_gpio: i2c1-gpio {
-				conf {
-					groups = "gpio0_24_grp", "gpio0_25_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				mux {
-					groups = "gpio0_24_grp", "gpio0_25_grp";
-					function = "gpio0";
-				};
-			};
-
-			pinctrl_gem3_default: gem3-default {
-				conf {
-					groups = "ethernet3_0_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				conf-rx {
-					pins = "MIO70", "MIO72", "MIO74";
-					bias-high-impedance;
-					low-power-disable;
-				};
-
-				conf-bootstrap {
-					pins = "MIO71", "MIO73", "MIO75";
-					bias-disable;
-					low-power-disable;
-				};
-
-				conf-tx {
-					pins = "MIO64", "MIO65", "MIO66",
-					       "MIO67", "MIO68", "MIO69";
-					bias-disable;
-					low-power-enable;
-				};
-
-				conf-mdio {
-					groups = "mdio3_0_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-					bias-disable;
-				};
-
-				mux-mdio {
-					function = "mdio3";
-					groups = "mdio3_0_grp";
-				};
-
-				mux {
-					function = "ethernet3";
-					groups = "ethernet3_0_grp";
-				};
-			};
-
-			pinctrl_usb0_default: usb0-default {
-				conf {
-					groups = "usb0_0_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				conf-rx {
-					pins = "MIO52", "MIO53", "MIO55";
-					bias-high-impedance;
-				};
-
-				conf-tx {
-					pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
-					"MIO60", "MIO61", "MIO62", "MIO63";
-					bias-disable;
-				};
-
-				mux {
-					groups = "usb0_0_grp";
-					function = "usb0";
-				};
-			};
-
-			pinctrl_sdhci1_default: sdhci1-default {
-				conf {
-					groups = "sdio1_0_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-					bias-disable;
-				};
-
-				conf-cd {
-					groups = "sdio1_cd_0_grp";
-					bias-high-impedance;
-					bias-pull-up;
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				mux-cd {
-					groups = "sdio1_cd_0_grp";
-					function = "sdio1_cd";
-				};
-
-				mux {
-					groups = "sdio1_0_grp";
-					function = "sdio1";
-				};
-			};
-		};
-	};
-	fragment15 {
-		target = <&uart1>;
-		__overlay__ {
-			status = "okay";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1_default>;
+		phy0: ethernet-phy@1 {
+			#phy-cells = <1>;
+			reg = <1>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+			ti,dp83867-rxctrl-strap-quirk;
 		};
 	};
 };
+
+&pinctrl0 { /* required by spec */
+	status = "okay";
+
+	pinctrl_uart1_default: uart1-default {
+		conf {
+			groups = "uart1_9_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+			drive-strength = <12>;
+		};
+
+		conf-rx {
+			pins = "MIO37";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO36";
+			bias-disable;
+		};
+
+		mux {
+			groups = "uart1_9_grp";
+			function = "uart1";
+		};
+	};
+
+	pinctrl_i2c1_default: i2c1-default {
+		conf {
+			groups = "i2c1_6_grp";
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux {
+			groups = "i2c1_6_grp";
+			function = "i2c1";
+		};
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpio {
+		conf {
+			groups = "gpio0_24_grp", "gpio0_25_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux {
+			groups = "gpio0_24_grp", "gpio0_25_grp";
+			function = "gpio0";
+		};
+	};
+
+	pinctrl_gem3_default: gem3-default {
+		conf {
+			groups = "ethernet3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO70", "MIO72", "MIO74";
+			bias-high-impedance;
+			low-power-disable;
+		};
+
+		conf-bootstrap {
+			pins = "MIO71", "MIO73", "MIO75";
+			bias-disable;
+			low-power-disable;
+		};
+
+		conf-tx {
+			pins = "MIO64", "MIO65", "MIO66",
+				"MIO67", "MIO68", "MIO69";
+			bias-disable;
+			low-power-enable;
+		};
+
+		conf-mdio {
+			groups = "mdio3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+
+		mux-mdio {
+			function = "mdio3";
+			groups = "mdio3_0_grp";
+		};
+
+		mux {
+			function = "ethernet3";
+			groups = "ethernet3_0_grp";
+		};
+	};
+
+	pinctrl_usb0_default: usb0-default {
+		conf {
+			groups = "usb0_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO52", "MIO53", "MIO55";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+			"MIO60", "MIO61", "MIO62", "MIO63";
+			bias-disable;
+		};
+
+		mux {
+			groups = "usb0_0_grp";
+			function = "usb0";
+		};
+	};
+
+	pinctrl_sdhci1_default: sdhci1-default {
+		conf {
+			groups = "sdio1_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+
+		conf-cd {
+			groups = "sdio1_cd_0_grp";
+			bias-high-impedance;
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux-cd {
+			groups = "sdio1_cd_0_grp";
+			function = "sdio1_cd";
+		};
+
+		mux {
+			groups = "sdio1_0_grp";
+			function = "sdio1";
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_default>;
+};
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@ -2,7 +2,7 @@
 /*
 * dts file for KV260 revA Carrier Card
 *
- * (C) Copyright 2020, Xilinx, Inc.
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -15,339 +15,304 @@
 /dts-v1/;
 /plugin/;

-/{
+&{/} {
 	compatible = "xlnx,zynqmp-sk-kv260-rev1",
-		     "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA",
+		     "xlnx,zynqmp-sk-kv260-revB",
 		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+};

-	fragment1 {
-		target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
+&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_default>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;

-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default", "gpio";
-			pinctrl-0 = <&pinctrl_i2c1_default>;
-			pinctrl-1 = <&pinctrl_i2c1_gpio>;
-			scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
-			sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+	u14: ina260@40 { /* u14 */
+		compatible = "ti,ina260";
+		#io-channel-cells = <1>;
+		label = "ina260-u14";
+		reg = <0x40>;
+	};
+	usbhub: usb5744@2d { /* u43 */
+		compatible = "microchip,usb5744";
+		reg = <0x2d>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+	};
+	/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+};

-			u14: ina260@40 { /* u14 */
-				compatible = "ti,ina260";
-				#io-channel-cells = <1>;
-				label = "ina260-u14";
-				reg = <0x40>;
-			};
-			usbhub: usb5744@2d { /* u43 */
-				compatible = "microchip,usb5744";
-				reg = <0x2d>;
-				reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
-			};
-			/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
-		};
+&amba {
+	ina260-u14 {
+		compatible = "iio-hwmon";
+		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
 	};

-	fragment1a {
-		target = <&amba>;
-		__overlay__ {
-			ina260-u14 {
-				compatible = "iio-hwmon";
-				io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
-			};
-
-			si5332_0: si5332_0 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <125000000>;
-			};
-
-			si5332_1: si5332_1 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <25000000>;
-			};
-
-			si5332_2: si5332_2 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <48000000>;
-			};
-
-			si5332_3: si5332_3 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <24000000>;
-			};
-
-			si5332_4: si5332_4 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <26000000>;
-			};
-
-			si5332_5: si5332_5 { /* u17 */
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <27000000>;
-			};
-		};
+	si5332_0: si5332_0 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
 	};

+	si5332_1: si5332_1 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	si5332_2: si5332_2 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <48000000>;
+	};
+
+	si5332_3: si5332_3 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
+
+	si5332_4: si5332_4 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+	};
+
+	si5332_5: si5332_5 { /* u17 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+};
+
 /* DP/USB 3.0 */
-	fragment2 {
-		target = <&psgtr>;
-		__overlay__ {
-			status = "okay";
-			/* pcie, usb3, sata */
-			clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
-			clock-names = "ref0", "ref1", "ref2";
-		};
-	};
+&psgtr {
+	status = "okay";
+	/* pcie, usb3, sata */
+	clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+	clock-names = "ref0", "ref1", "ref2";
+};

-	fragment4 {
-		target = <&zynqmp_dpsub>;
-		__overlay__ {
-			status = "disabled";
-			phy-names = "dp-phy0", "dp-phy1";
-			phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
-		};
-	};
+&zynqmp_dpsub {
+	status = "disabled";
+	phy-names = "dp-phy0", "dp-phy1";
+	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+};

-	fragment9 {
-		target = <&zynqmp_dpdma>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
+&zynqmp_dpdma {
+	status = "okay";
+};

-	fragment10 {
-		target = <&usb0>;
-		__overlay__ {
-			status = "okay";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb0_default>;
-		};
-	};
+&usb0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0_default>;
+};

-	fragment11 {
-		target = <&dwc3_0>;
-		__overlay__ {
-			status = "okay";
-			dr_mode = "host";
-			snps,usb3_lpm_capable;
-			phy-names = "usb3-phy";
-			phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
-			maximum-speed = "super-speed";
-		};
-	};
+&dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+	snps,usb3_lpm_capable;
+	phy-names = "usb3-phy";
+	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+	maximum-speed = "super-speed";
+};

-	fragment12 {
-		target = <&sdhci1>; /* on CC with tuned parameters */
-		__overlay__ {
-			status = "okay";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_sdhci1_default>;
-			/*
-			 * SD 3.0 requires level shifter and this property
-			 * should be removed if the board has level shifter and
-			 * need to work in UHS mode
-			 */
-			no-1-8-v;
-			disable-wp;
-			xlnx,mio-bank = <1>;
-			clk-phase-sd-hs = <126>, <60>;
-			clk-phase-uhs-sdr25 = <120>, <60>;
-			clk-phase-uhs-ddr50 = <126>, <48>;
-		};
-	};
+&sdhci1 { /* on CC with tuned parameters */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci1_default>;
+	/*
+	 * SD 3.0 requires level shifter and this property
+	 * should be removed if the board has level shifter and
+	 * need to work in UHS mode
+	 */
+	no-1-8-v;
+	disable-wp;
+	xlnx,mio-bank = <1>;
+	clk-phase-sd-hs = <126>, <60>;
+	clk-phase-uhs-sdr25 = <120>, <60>;
+	clk-phase-uhs-ddr50 = <126>, <48>;
+};

-	fragment13 {
-		target = <&gem3>; /* required by spec */
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "okay";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_gem3_default>;
-			phy-handle = <&phy0>;
-			phy-mode = "rgmii-id";
+&gem3 { /* required by spec */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gem3_default>;
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";

-			mdio: mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
-				reset-delay-us = <2>;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <2>;

-				phy0: ethernet-phy@1 {
-					#phy-cells = <1>;
-					reg = <1>;
-					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
-					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
-					ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-					ti,dp83867-rxctrl-strap-quirk;
-				};
-			};
-		};
-	};
-
-	fragment14 {
-		target = <&pinctrl0>; /* required by spec */
-		__overlay__ {
-			status = "okay";
-
-			pinctrl_uart1_default: uart1-default {
-				conf {
-					groups = "uart1_9_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-					drive-strength = <12>;
-				};
-
-				conf-rx {
-					pins = "MIO37";
-					bias-high-impedance;
-				};
-
-				conf-tx {
-					pins = "MIO36";
-					bias-disable;
-				};
-
-				mux {
-					groups = "uart1_9_grp";
-					function = "uart1";
-				};
-			};
-
-			pinctrl_i2c1_default: i2c1-default {
-				conf {
-					groups = "i2c1_6_grp";
-					bias-pull-up;
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				mux {
-					groups = "i2c1_6_grp";
-					function = "i2c1";
-				};
-			};
-
-			pinctrl_i2c1_gpio: i2c1-gpio {
-				conf {
-					groups = "gpio0_24_grp", "gpio0_25_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				mux {
-					groups = "gpio0_24_grp", "gpio0_25_grp";
-					function = "gpio0";
-				};
-			};
-
-			pinctrl_gem3_default: gem3-default {
-				conf {
-					groups = "ethernet3_0_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				conf-rx {
-					pins = "MIO70", "MIO72", "MIO74";
-					bias-high-impedance;
-					low-power-disable;
-				};
-
-				conf-bootstrap {
-					pins = "MIO71", "MIO73", "MIO75";
-					bias-disable;
-					low-power-disable;
-				};
-
-				conf-tx {
-					pins = "MIO64", "MIO65", "MIO66",
-					       "MIO67", "MIO68", "MIO69";
-					bias-disable;
-					low-power-enable;
-				};
-
-				conf-mdio {
-					groups = "mdio3_0_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-					bias-disable;
-				};
-
-				mux-mdio {
-					function = "mdio3";
-					groups = "mdio3_0_grp";
-				};
-
-				mux {
-					function = "ethernet3";
-					groups = "ethernet3_0_grp";
-				};
-			};
-
-			pinctrl_usb0_default: usb0-default {
-				conf {
-					groups = "usb0_0_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				conf-rx {
-					pins = "MIO52", "MIO53", "MIO55";
-					bias-high-impedance;
-				};
-
-				conf-tx {
-					pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
-					"MIO60", "MIO61", "MIO62", "MIO63";
-					bias-disable;
-				};
-
-				mux {
-					groups = "usb0_0_grp";
-					function = "usb0";
-				};
-			};
-
-			pinctrl_sdhci1_default: sdhci1-default {
-				conf {
-					groups = "sdio1_0_grp";
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-					bias-disable;
-				};
-
-				conf-cd {
-					groups = "sdio1_cd_0_grp";
-					bias-high-impedance;
-					bias-pull-up;
-					slew-rate = <SLEW_RATE_SLOW>;
-					power-source = <IO_STANDARD_LVCMOS18>;
-				};
-
-				mux-cd {
-					groups = "sdio1_cd_0_grp";
-					function = "sdio1_cd";
-				};
-
-				mux {
-					groups = "sdio1_0_grp";
-					function = "sdio1";
-				};
-			};
-		};
-	};
-	fragment15 {
-		target = <&uart1>;
-		__overlay__ {
-			status = "okay";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1_default>;
+		phy0: ethernet-phy@1 {
+			#phy-cells = <1>;
+			reg = <1>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+			ti,dp83867-rxctrl-strap-quirk;
 		};
 	};
 };
+
+&pinctrl0 { /* required by spec */
+	status = "okay";
+
+	pinctrl_uart1_default: uart1-default {
+		conf {
+			groups = "uart1_9_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+			drive-strength = <12>;
+		};
+
+		conf-rx {
+			pins = "MIO37";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO36";
+			bias-disable;
+		};
+
+		mux {
+			groups = "uart1_9_grp";
+			function = "uart1";
+		};
+	};
+
+	pinctrl_i2c1_default: i2c1-default {
+		conf {
+			groups = "i2c1_6_grp";
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux {
+			groups = "i2c1_6_grp";
+			function = "i2c1";
+		};
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpio {
+		conf {
+			groups = "gpio0_24_grp", "gpio0_25_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux {
+			groups = "gpio0_24_grp", "gpio0_25_grp";
+			function = "gpio0";
+		};
+	};
+
+	pinctrl_gem3_default: gem3-default {
+		conf {
+			groups = "ethernet3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO70", "MIO72", "MIO74";
+			bias-high-impedance;
+			low-power-disable;
+		};
+
+		conf-bootstrap {
+			pins = "MIO71", "MIO73", "MIO75";
+			bias-disable;
+			low-power-disable;
+		};
+
+		conf-tx {
+			pins = "MIO64", "MIO65", "MIO66",
+				"MIO67", "MIO68", "MIO69";
+			bias-disable;
+			low-power-enable;
+		};
+
+		conf-mdio {
+			groups = "mdio3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+
+		mux-mdio {
+			function = "mdio3";
+			groups = "mdio3_0_grp";
+		};
+
+		mux {
+			function = "ethernet3";
+			groups = "ethernet3_0_grp";
+		};
+	};
+
+	pinctrl_usb0_default: usb0-default {
+		conf {
+			groups = "usb0_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO52", "MIO53", "MIO55";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+			"MIO60", "MIO61", "MIO62", "MIO63";
+			bias-disable;
+		};
+
+		mux {
+			groups = "usb0_0_grp";
+			function = "usb0";
+		};
+	};
+
+	pinctrl_sdhci1_default: sdhci1-default {
+		conf {
+			groups = "sdio1_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+
+		conf-cd {
+			groups = "sdio1_cd_0_grp";
+			bias-high-impedance;
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux-cd {
+			groups = "sdio1_cd_0_grp";
+			function = "sdio1_cd";
+		};
+
+		mux {
+			groups = "sdio1_0_grp";
+			function = "sdio1";
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_default>;
+};
--- a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
+++ b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP K26/KV260 SD wiring
 *
- * (C) Copyright 2020, Xilinx, Inc.
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
 *
- * (C) Copyright 2020, Xilinx, Inc.
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -22,11 +22,12 @@
 		     "xlnx,zynqmp";

 	aliases {
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
+		nvmem0 = &eeprom;
+		nvmem1 = &eeprom_cc;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -36,8 +37,6 @@
 		spi2 = &spi1;
 		usb0 = &usb0;
 		usb1 = &usb1;
-		nvmem0 = &eeprom;
-		nvmem1 = &eeprom_cc;
 	};

 	chosen {
--- a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
+++ b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP Z2-VSOM
 *
- * (C) Copyright 2020, Xilinx, Inc.
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
--- a/arch/arm/dts/zynqmp-smk-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
 *
- * (C) Copyright 2020, Xilinx, Inc.
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
--- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
@ -19,7 +19,6 @@
 		     "topic,miamimp", "xlnx,zynqmp";

 	aliases {
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci0;
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZC1232
 *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -11,7 +11,6 @@

 #include "zynqmp.dtsi"
 #include "zynqmp-clk-ccf.dtsi"
-#include <dt-bindings/phy/phy.h>

 / {
 	model = "ZynqMP ZC1232 RevA";
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
 *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -21,7 +21,6 @@

 	aliases {
 		ethernet0 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c1;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
@ -60,13 +59,6 @@
 	};
 };

-&psgtr {
-	status = "okay";
-	/* dp, usb3, sata */
-	clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
-	clock-names = "ref1", "ref2", "ref3";
-};
-
 &fpd_dma_chan1 {
 	status = "okay";
 };
@ -345,6 +337,13 @@
 	};
 };

+&psgtr {
+	status = "okay";
+	/* dp, usb3, sata */
+	clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
 &qspi {
 	status = "okay";
 	flash@0 {
@ -433,6 +432,7 @@
 	snps,usb3_lpm_capable;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+	maximum-speed = "super-speed";
 };

 &zynqmp_dpdma {
@ -441,5 +441,7 @@

 &zynqmp_dpsub {
 	status = "okay";
+	phy-names = "dp-phy0", "dp-phy1";
+	phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
+	       <&psgtr 0 PHY_TYPE_DP 1 1>;
 };
-
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
 *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -19,10 +19,7 @@
 	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";

 	aliases {
-		can0 = &can0;
-		can1 = &can1;
 		ethernet0 = &gem2;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		rtc0 = &rtc;
 		serial0 = &uart0;
@ -538,6 +535,8 @@
 &dwc3_1 {
 	status = "okay";
 	dr_mode = "host";
+	snps,usb3_lpm_capable;
+	maximum-speed = "super-speed";
 };

 &uart0 {
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
 *
- * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -11,6 +11,7 @@

 #include "zynqmp.dtsi"
 #include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/phy/phy.h>

 / {
 	model = "ZynqMP zc1751-xm017-dc3 RevA";
@ -18,7 +19,6 @@

 	aliases {
 		ethernet0 = &gem0;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci1;
@ -38,6 +38,18 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
+
+	clock_si5338_2: clk26 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+	};
+
+	clock_si5338_3: clk125 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
 };

 &fpd_dma_chan1 {
@ -167,6 +179,13 @@
 	};
 };

+&psgtr {
+	status = "okay";
+	/* usb3, sata */
+	clocks = <&clock_si5338_2>, <&clock_si5338_3>;
+	clock-names = "ref2", "ref3";
+};
+
 &rtc {
 	status = "okay";
 };
@ -182,6 +201,8 @@
 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
 };

 &sdhci1 { /* emmc with some settings */
@ -200,11 +221,27 @@

 &usb0 {
 	status = "okay";
+};
+
+&dwc3_0 {
+	status = "okay";
 	dr_mode = "host";
+	snps,usb3_lpm_capable;
+	phy-names = "usb3-phy";
+	phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
+	maximum-speed = "super-speed";
 };

 /* ULPI SMSC USB3320 */
 &usb1 {
 	status = "okay";
-	dr_mode = "host";
+};
+
+&dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+	snps,usb3_lpm_capable;
+	phy-names = "usb3-phy";
+	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
+	maximum-speed = "super-speed";
 };
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
 *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -17,13 +17,10 @@
 	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";

 	aliases {
-		can0 = &can0;
-		can1 = &can1;
 		ethernet0 = &gem0;
 		ethernet1 = &gem1;
 		ethernet2 = &gem2;
 		ethernet3 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		rtc0 = &rtc;
@ -115,14 +112,6 @@
 	status = "okay";
 };

-&zynqmp_dpsub {
-	status = "okay";
-};
-
-&zynqmp_dpdma {
-	status = "okay";
-};
-
 &gem0 {
 	status = "okay";
 	phy-mode = "rgmii-id";
@ -221,3 +210,11 @@
 &watchdog0 {
 	status = "okay";
 };
+
+&zynqmp_dpdma {
+	status = "okay";
+};
+
+&zynqmp_dpsub {
+	status = "okay";
+};
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
 *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
 * Michal Simek <michal.simek@xilinx.com>
@ -21,7 +21,6 @@

 	aliases {
 		ethernet0 = &gem1;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci0;
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU100 revC
 *
- * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 * Nathalie Chan King Choy
@ -23,7 +23,6 @@
 	compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";

 	aliases {
-		gpio0 = &gpio;
 		i2c0 = &i2c1;
 		rtc0 = &rtc;
 		serial0 = &uart1;
@ -132,13 +131,13 @@
 		io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
 	};

-	si5335a_0: clk26 {
+	si5335_0: si5335_0 { /* clk0_usb - u23 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <26000000>;
 	};

-	si5335a_1: clk27 {
+	si5335_1: si5335_1 { /* clk1_dp - u23 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <27000000>;
@ -485,8 +484,8 @@

 &psgtr {
 	status = "okay";
-	/* usb3, dps */
-	clocks = <&si5335a_0>, <&si5335a_1>;
+	/* usb3, dp */
+	clocks = <&si5335_0>, <&si5335_1>;
 	clock-names = "ref0", "ref1";
 };

--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU102 RevA
 *
- * (C) Copyright 2015 - 2020, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -22,10 +22,10 @@

 	aliases {
 		ethernet0 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -37,7 +37,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = &eeprom;
 	};

 	memory@0 {
@ -605,15 +604,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <4>;
-			si5328: clock-generator@69 {/* SI5328 - u20 */
-				compatible = "silabs,si5328";
-				reg = <0x69>;
-				/*
-				 * Chip has interrupt present connected to PL
-				 * interrupt-parent = <&>;
-				 * interrupts = <>;
-				 */
-			};
+			/* SI5328 - u20 */
 		};
 		/* 5 - 7 unconnected */
 	};
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU104
 *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -21,9 +21,9 @@

 	aliases {
 		ethernet0 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c1;
 		mmc0 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -165,10 +165,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <1>;
-			clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
-				compatible = "idt,8t49n287";
-				reg = <0x6c>;
-			};
+			/* 8T49N287 - u182 */
 		};

 		i2c@2 {
@ -423,6 +420,13 @@
 	};
 };

+&psgtr {
+	status = "okay";
+	/* nc, sata, usb3, dp */
+	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
 &qspi {
 	status = "okay";
 	flash@0 {
@ -452,13 +456,6 @@
 	};
 };

-&psgtr {
-	status = "okay";
-	/* nc, sata, usb3, dp */
-	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
-	clock-names = "ref1", "ref2", "ref3";
-};
-
 &rtc {
 	status = "okay";
 };
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU104
 *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -21,9 +21,9 @@

 	aliases {
 		ethernet0 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c1;
 		mmc0 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -35,7 +35,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = &eeprom;
 	};

 	memory@0 {
@ -190,10 +189,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <1>;
-			clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
-				compatible = "idt,8t49n287";
-				reg = <0x6c>;
-			};
+			/* 8T49N287 - u182 */
 		};

 		i2c@2 {
@ -436,6 +432,13 @@
 	};
 };

+&psgtr {
+	status = "okay";
+	/* nc, sata, usb3, dp */
+	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
 &qspi {
 	status = "okay";
 	flash@0 {
@ -469,13 +472,6 @@
 	status = "okay";
 };

-&psgtr {
-	status = "okay";
-	/* nc, sata, usb3, dp */
-	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
-	clock-names = "ref1", "ref2", "ref3";
-};
-
 &sata {
 	status = "okay";
 	/* SATA OOB timing settings */
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU106
 *
- * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -22,10 +22,10 @@

 	aliases {
 		ethernet0 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &uart1;
@ -37,7 +37,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = &eeprom;
 	};

 	memory@0 {
@ -163,18 +162,6 @@
 	status = "okay";
 };

-&zynqmp_dpdma {
-	status = "okay";
-};
-
-&zynqmp_dpsub {
-	status = "okay";
-	phy-names = "dp-phy0", "dp-phy1";
-	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
-	       <&psgtr 0 PHY_TYPE_DP 1 3>;
-};
-
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
 	status = "okay";
 };
@ -606,25 +593,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <4>;
-			si5328: clock-generator@69 {/* SI5328 - u20 */
-				reg = <0x69>;
-				/*
-				 * Chip has interrupt present connected to PL
-				 * interrupt-parent = <&>;
-				 * interrupts = <>;
-				 */
-				#address-cells = <1>;
-				#size-cells = <0>;
-				#clock-cells = <1>;
-				clocks = <&refhdmi>;
-				clock-names = "xtal";
-				clock-output-names = "si5328";
-
-				si5328_clk: clk0@0 {
-					reg = <0>;
-					clock-frequency = <27000000>;
-				};
-			};
+			/* SI5328 - u20 */
 		};
 		i2c@5 {
 			#address-cells = <1>;
@ -1051,8 +1020,20 @@
 	snps,usb3_lpm_capable;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+	maximum-speed = "super-speed";
 };

 &watchdog0 {
 	status = "okay";
 };
+
+&zynqmp_dpdma {
+	status = "okay";
+};
+
+&zynqmp_dpsub {
+	status = "okay";
+	phy-names = "dp-phy0", "dp-phy1";
+	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+	       <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU111
 *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -22,10 +22,10 @@

 	aliases {
 		ethernet0 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &dcc;
@ -36,7 +36,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = &eeprom;
 	};

 	memory@0 {
@ -481,10 +480,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <4>;
-			si5382: clock-generator@69 { /* SI5382 - u48 */
-				compatible = "silabs,si5382";
-				reg = <0x69>;
-			};
+			/* SI5382 - u48 */
 		};
 		i2c@5 {
 			#address-cells = <1>;
@ -775,8 +771,8 @@

 &psgtr {
 	status = "okay";
-	/* nc, sata, usb3, dp */
-	clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+	/* nc, dp, usb3, sata */
+	clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
 	clock-names = "ref1", "ref2", "ref3";
 };

@ -861,6 +857,7 @@
 	snps,usb3_lpm_capable;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+	maximum-speed = "super-speed";
 };

 &zynqmp_dpdma {
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU1275
 *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -39,6 +39,10 @@
 	status = "okay";
 };

+&gpio {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 	flash@0 {
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU1275 RevB
 *
- * (C) Copyright 2018 - 2020, Xilinx, Inc.
+ * (C) Copyright 2018 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -64,6 +64,10 @@
 	};
 };

+&gpio {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 	flash@0 {
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU1285 RevA
 *
- * (C) Copyright 2018 - 2020, Xilinx, Inc.
+ * (C) Copyright 2018 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -245,6 +245,10 @@
 	};
 };

+&gpio {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 	flash@0 {
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU208
 *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -22,10 +22,10 @@

 	aliases {
 		ethernet0 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &dcc;
@ -36,7 +36,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = &eeprom;
 	};

 	memory@0 {
@ -651,9 +650,9 @@

 &psgtr {
 	status = "okay";
-	/* pcie, sata, usb3, dp */
-	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
-	clock-names = "ref0", "ref1", "ref2", "ref3";
+	/* nc, nc, usb3, sata */
+	clocks = <&si5341 0 2>, <&si5341 0 3>;
+	clock-names = "ref2", "ref3";
 };

 &rtc {
@ -701,4 +700,5 @@
 	snps,usb3_lpm_capable;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+	maximum-speed = "super-speed";
 };
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP ZCU216
 *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@ -22,10 +22,10 @@

 	aliases {
 		ethernet0 = &gem3;
-		gpio0 = &gpio;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		mmc0 = &sdhci1;
+		nvmem0 = &eeprom;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &dcc;
@ -36,7 +36,6 @@
 	chosen {
 		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
-		xlnx,eeprom = <&eeprom>;
 	};

 	memory@0 {
@ -132,9 +131,9 @@

 &psgtr {
 	status = "okay";
-	/* pcie, sata, usb3, dp */
-	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
-	clock-names = "ref0", "ref1", "ref2", "ref3";
+	/* nc, nc, usb3, sata */
+	clocks = <&si5341 0 2>, <&si5341 0 3>;
+	clock-names = "ref2", "ref3";
 };

 &dcc {
@ -705,4 +704,5 @@
 	snps,usb3_lpm_capable;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+	maximum-speed = "super-speed";
 };
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@ -2,7 +2,7 @@
 /*
 * dts file for Xilinx ZynqMP
 *
- * (C) Copyright 2014 - 2020, Xilinx, Inc.
+ * (C) Copyright 2014 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 *
@ -100,7 +100,7 @@
 		};
 	};

-	zynqmp_ipi {
+	zynqmp_ipi: zynqmp_ipi {
 		u-boot,dm-pre-reloc;
 		compatible = "xlnx,zynqmp-ipi-mailbox";
 		interrupt-parent = <&gic>;
@ -246,6 +246,7 @@

 		cci: cci@fd6e0000 {
 			compatible = "arm,cci-400";
+			status = "disabled";
 			reg = <0x0 0xfd6e0000 0x0 0x9000>;
 			ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 			#address-cells = <1>;
@ -647,6 +648,8 @@
 					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x4d0>;
 			power-domains = <&zynqmp_firmware PD_PCIE>;
 			pcie_intc: legacy-interrupt-controller {
 				interrupt-controller;
@ -688,7 +691,7 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 26 4>, <0 27 4>;
 			interrupt-names = "alarm", "sec";
-			calibration = <0x8000>;
+			calibration = <0x7FFF>;
 		};

 		sata: ahci@fd0c0000 {
@ -698,6 +701,7 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 133 4>;
 			power-domains = <&zynqmp_firmware PD_SATA>;
+			resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
 			#stream-id-cells = <4>;
 			iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 				 <&smmu 0x4c2>, <&smmu 0x4c3>;
@ -715,8 +719,6 @@
 			xlnx,device_id = <0>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x870>;
-			nvmem-cells = <&soc_revision>;
-			nvmem-cell-names = "soc_revision";
 			#clock-cells = <1>;
 			clock-output-names = "clk_out_sd0", "clk_in_sd0";
 			power-domains = <&zynqmp_firmware PD_SD_0>;
@ -733,8 +735,6 @@
 			xlnx,device_id = <1>;
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x871>;
-			nvmem-cells = <&soc_revision>;
-			nvmem-cell-names = "soc_revision";
 			#clock-cells = <1>;
 			clock-output-names = "clk_out_sd1", "clk_in_sd1";
 			power-domains = <&zynqmp_firmware PD_SD_1>;
@ -848,20 +848,26 @@
 			reg = <0x0 0xff9d0000 0x0 0x100>;
 			clock-names = "bus_clk", "ref_clk";
 			power-domains = <&zynqmp_firmware PD_USB_0>;
+			resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
+				 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
+				 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
+			reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
 			ranges;
-			nvmem-cells = <&soc_revision>;
-			nvmem-cell-names = "soc_revision";

 			dwc3_0: dwc3@fe200000 {
 				compatible = "snps,dwc3";
 				status = "disabled";
 				reg = <0x0 0xfe200000 0x0 0x40000>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 65 4>, <0 69 4>;
+				interrupt-names = "dwc_usb3", "otg", "hiber";
+				interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
 				#stream-id-cells = <1>;
 				iommus = <&smmu 0x860>;
 				snps,quirk-frame-length-adjustment = <0x20>;
 				snps,refclk_fladj;
+				snps,enable_guctl1_resume_quirk;
+				snps,enable_guctl1_ipd_quirk;
+				snps,xhci-stream-quirk;
 				/* dma-coherent; */
 			};
 		};
@ -874,20 +880,26 @@
 			reg = <0x0 0xff9e0000 0x0 0x100>;
 			clock-names = "bus_clk", "ref_clk";
 			power-domains = <&zynqmp_firmware PD_USB_1>;
+			resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
+				 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
+				 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
+			reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
 			ranges;
-			nvmem-cells = <&soc_revision>;
-			nvmem-cell-names = "soc_revision";

 			dwc3_1: dwc3@fe300000 {
 				compatible = "snps,dwc3";
 				status = "disabled";
 				reg = <0x0 0xfe300000 0x0 0x40000>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 70 4>, <0 74 4>;
+				interrupt-names = "dwc_usb3", "otg", "hiber";
+				interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
 				#stream-id-cells = <1>;
 				iommus = <&smmu 0x861>;
 				snps,quirk-frame-length-adjustment = <0x20>;
 				snps,refclk_fladj;
+				snps,enable_guctl1_resume_quirk;
+				snps,enable_guctl1_ipd_quirk;
+				snps,xhci-stream-quirk;
 				/* dma-coherent; */
 			};
 		};
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@ -92,6 +92,41 @@ config ZYNQMP_NO_DDR
 	  This option configures MMU with no DDR to avoid speculative
 	  access to DDR memory where DDR is not present.

+config SPL_ZYNQMP_DRAM_ECC_INIT
+	bool "Initialize DRAM ECC"
+	depends on SPL
+	help
+	  This option initializes all memory to 0xdeadbeef. Must be set if your
+	  memory is of ECC type.
+
+config SPL_ZYNQMP_DRAM_BANK1_BASE
+	depends on SPL_ZYNQMP_DRAM_ECC_INIT
+	hex "DRAM Bank1 address"
+       default 0x00000000
+       help
+         Start address of DRAM ECC bank1
+
+config SPL_ZYNQMP_DRAM_BANK1_LEN
+	depends on SPL_ZYNQMP_DRAM_ECC_INIT
+	hex "DRAM Bank1 size"
+       default 0x80000000
+       help
+         Size in bytes of the DRAM ECC bank1
+
+config SPL_ZYNQMP_DRAM_BANK2_BASE
+	depends on SPL_ZYNQMP_DRAM_ECC_INIT
+	hex "DRAM Bank2 address"
+       default 0x800000000
+       help
+         Start address of DRAM ECC bank2
+
+config SPL_ZYNQMP_DRAM_BANK2_LEN
+	depends on SPL_ZYNQMP_DRAM_ECC_INIT
+	hex "DRAM Bank2 size"
+       default 0x0
+       help
+         Size in bytes of the DRAM ECC bank2. A null size takes no action.
+
 config SYS_MALLOC_F_LEN
 	default 0x600

--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@ -7,4 +7,5 @@ obj-y	+= clk.o
 obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
 obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
+obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
 obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED)	+= psu_spl_init.o
--- a/arch/arm/mach-zynqmp/ecc_spl_init.c
+++ b/arch/arm/mach-zynqmp/ecc_spl_init.c
@ -0,0 +1,163 @@
+// SPDX-License-Identifier: MIT
+/*
+ *  Copyright(c) 2015 - 2020 Xilinx, Inc.
+ *
+ *  Jorge Ramirez-Ortiz <jorge@foundries.io>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ecc_spl_init.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#define ZDMA_TRANSFER_MAX_LEN		(0x3FFFFFFFU - 7U)
+#define ZDMA_CH_STATUS			((ADMA_CH0_BASEADDR) + 0x0000011CU)
+#define ZDMA_CH_STATUS_STATE_MASK	0x00000003U
+#define ZDMA_CH_STATUS_STATE_DONE	0x00000000U
+#define ZDMA_CH_STATUS_STATE_ERR	0x00000003U
+#define ZDMA_CH_CTRL0			((ADMA_CH0_BASEADDR) + 0x00000110U)
+#define ZDMA_CH_CTRL0_POINT_TYPE_MASK	(u32)0x00000040U
+#define ZDMA_CH_CTRL0_POINT_TYPE_NORMAL	(u32)0x00000000U
+#define ZDMA_CH_CTRL0_MODE_MASK		(u32)0x00000030U
+#define ZDMA_CH_CTRL0_MODE_WR_ONLY	(u32)0x00000010U
+#define ZDMA_CH_CTRL0_TOTAL_BYTE_COUNT	((ADMA_CH0_BASEADDR) + 0x00000188U)
+#define ZDMA_CH_WR_ONLY_WORD0		((ADMA_CH0_BASEADDR) + 0x00000148U)
+#define ZDMA_CH_WR_ONLY_WORD1		((ADMA_CH0_BASEADDR) + 0x0000014CU)
+#define ZDMA_CH_WR_ONLY_WORD2		((ADMA_CH0_BASEADDR) + 0x00000150U)
+#define ZDMA_CH_WR_ONLY_WORD3		((ADMA_CH0_BASEADDR) + 0x00000154U)
+#define ZDMA_CH_DST_DSCR_WORD0		((ADMA_CH0_BASEADDR) + 0x00000138U)
+#define ZDMA_CH_DST_DSCR_WORD0_LSB_MASK	0xFFFFFFFFU
+#define ZDMA_CH_DST_DSCR_WORD1		((ADMA_CH0_BASEADDR) + 0x0000013CU)
+#define ZDMA_CH_DST_DSCR_WORD1_MSB_MASK	0x0001FFFFU
+#define ZDMA_CH_SRC_DSCR_WORD2		((ADMA_CH0_BASEADDR) + 0x00000130U)
+#define ZDMA_CH_DST_DSCR_WORD2		((ADMA_CH0_BASEADDR) + 0x00000140U)
+#define ZDMA_CH_CTRL2			((ADMA_CH0_BASEADDR) + 0x00000200U)
+#define ZDMA_CH_CTRL2_EN_MASK		0x00000001U
+#define ZDMA_CH_ISR			((ADMA_CH0_BASEADDR) + 0x00000100U)
+#define ZDMA_CH_ISR_DMA_DONE_MASK	0x00000400U
+#define ECC_INIT_VAL_WORD		0xDEADBEEFU
+
+#define ZDMA_IDLE_TIMEOUT_USEC		1000000
+#define ZDMA_DONE_TIMEOUT_USEC		5000000
+
+static void ecc_zdma_restore(void)
+{
+	/* Restore reset values for the DMA registers used */
+	writel(ZDMA_CH_CTRL0, 0x00000080U);
+	writel(ZDMA_CH_WR_ONLY_WORD0, 0x00000000U);
+	writel(ZDMA_CH_WR_ONLY_WORD1, 0x00000000U);
+	writel(ZDMA_CH_WR_ONLY_WORD2, 0x00000000U);
+	writel(ZDMA_CH_WR_ONLY_WORD3, 0x00000000U);
+	writel(ZDMA_CH_DST_DSCR_WORD0, 0x00000000U);
+	writel(ZDMA_CH_DST_DSCR_WORD1, 0x00000000U);
+	writel(ZDMA_CH_SRC_DSCR_WORD2, 0x00000000U);
+	writel(ZDMA_CH_DST_DSCR_WORD2, 0x00000000U);
+	writel(ZDMA_CH_CTRL0_TOTAL_BYTE_COUNT, 0x00000000U);
+}
+
+static void ecc_dram_bank_init(u64 addr, u64 len)
+{
+	bool retry = true;
+	u32 timeout;
+	u64 bytes;
+	u32 size;
+	u64 src;
+	u32 reg;
+
+	if (!len)
+		return;
+retry:
+	bytes = len;
+	src = addr;
+	ecc_zdma_restore();
+	while (bytes > 0) {
+		size = bytes > ZDMA_TRANSFER_MAX_LEN ?
+			ZDMA_TRANSFER_MAX_LEN : (u32)bytes;
+
+		/* Wait until the DMA is in idle state */
+		timeout = ZDMA_IDLE_TIMEOUT_USEC;
+		do {
+			udelay(1);
+			reg = readl(ZDMA_CH_STATUS);
+			reg &= ZDMA_CH_STATUS_STATE_MASK;
+			if (!timeout--) {
+				puts("error, ECC DMA failed to idle\n");
+				goto done;
+			}
+
+		} while ((reg != ZDMA_CH_STATUS_STATE_DONE) &&
+			(reg != ZDMA_CH_STATUS_STATE_ERR));
+
+		/* Enable Simple (Write Only) Mode */
+		reg = readl(ZDMA_CH_CTRL0);
+		reg &= (ZDMA_CH_CTRL0_POINT_TYPE_MASK |
+			ZDMA_CH_CTRL0_MODE_MASK);
+		reg |= (ZDMA_CH_CTRL0_POINT_TYPE_NORMAL |
+			ZDMA_CH_CTRL0_MODE_WR_ONLY);
+		writel(reg, ZDMA_CH_CTRL0);
+
+		/* Fill in the data to be written */
+		writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD0);
+		writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD1);
+		writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD2);
+		writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD3);
+
+		/* Write Destination Address */
+		writel((u32)(src & ZDMA_CH_DST_DSCR_WORD0_LSB_MASK),
+		       ZDMA_CH_DST_DSCR_WORD0);
+		writel((u32)((src >> 32) & ZDMA_CH_DST_DSCR_WORD1_MSB_MASK),
+		       ZDMA_CH_DST_DSCR_WORD1);
+
+		/* Size to be Transferred. Recommended to set both src and dest sizes */
+		writel(size, ZDMA_CH_SRC_DSCR_WORD2);
+		writel(size, ZDMA_CH_DST_DSCR_WORD2);
+
+		/* DMA Enable */
+		reg = readl(ZDMA_CH_CTRL2);
+		reg |= ZDMA_CH_CTRL2_EN_MASK;
+		writel(reg, ZDMA_CH_CTRL2);
+
+		/* Check the status of the transfer by polling on DMA Done */
+		timeout = ZDMA_DONE_TIMEOUT_USEC;
+		do {
+			udelay(1);
+			reg = readl(ZDMA_CH_ISR);
+			reg &= ZDMA_CH_ISR_DMA_DONE_MASK;
+			if (!timeout--) {
+				puts("error, ECC DMA timeout\n");
+				goto done;
+			}
+		} while (reg != ZDMA_CH_ISR_DMA_DONE_MASK);
+
+		/* Clear DMA status */
+		reg = readl(ZDMA_CH_ISR);
+		reg |= ZDMA_CH_ISR_DMA_DONE_MASK;
+		writel(ZDMA_CH_ISR_DMA_DONE_MASK, ZDMA_CH_ISR);
+
+		/* Read the channel status for errors */
+		reg = readl(ZDMA_CH_STATUS);
+		if (reg == ZDMA_CH_STATUS_STATE_ERR) {
+			if (retry) {
+				retry = false;
+				goto retry;
+			}
+			puts("error, ECC DMA error\n");
+			break;
+		}
+
+		bytes -= size;
+		src += size;
+	}
+done:
+	ecc_zdma_restore();
+}
+
+void zynqmp_ecc_init(void)
+{
+	ecc_dram_bank_init(CONFIG_SPL_ZYNQMP_DRAM_BANK1_BASE,
+			   CONFIG_SPL_ZYNQMP_DRAM_BANK1_LEN);
+	ecc_dram_bank_init(CONFIG_SPL_ZYNQMP_DRAM_BANK2_BASE,
+			   CONFIG_SPL_ZYNQMP_DRAM_BANK2_LEN);
+}
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@ -71,6 +71,7 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
 					     uintptr_t fdt_addr)
 {
 	struct xfsbl_atf_handoff_params *atfhandoffparams;
+	u32 index = 0;

 	atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE;
 	atfhandoffparams->magic[0] = 'X';
@ -78,14 +79,22 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
 	atfhandoffparams->magic[2] = 'N';
 	atfhandoffparams->magic[3] = 'X';

-	atfhandoffparams->num_entries = 0;
-	if (bl33_entry) {
-		atfhandoffparams->partition[0].entry_point = bl33_entry;
-		atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
-						       FSBL_FLAGS_EL_SHIFT;
-		atfhandoffparams->num_entries++;
+	if (bl32_entry) {
+		atfhandoffparams->partition[index].entry_point = bl32_entry;
+		atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL1 << FSBL_FLAGS_EL_SHIFT |
+							   FSBL_FLAGS_SECURE << FSBL_FLAGS_TZ_SHIFT;
+		index++;
 	}

+	if (bl33_entry) {
+		atfhandoffparams->partition[index].entry_point = bl33_entry;
+		atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL2 <<
+							   FSBL_FLAGS_EL_SHIFT;
+		index++;
+	}
+
+	atfhandoffparams->num_entries = index;
+
 	writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6);

 	return NULL;
--- a/arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h
+++ b/arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h
@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ *  Copyright(c) 2015 - 2020 Xilinx, Inc.
+ *
+ *  Jorge Ramirez-Ortiz <jorge@foundries.io>
+ */
+
+#ifndef __ARCH_ZYNQMP_ECC_INIT_H
+#define __ARCH_ZYNQMP_ECC_INIT_H
+
+void zynqmp_ecc_init(void);
+
+#endif
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@ -24,6 +24,8 @@
 							    + 0x00000114)
 #define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210

+#define ADMA_CH0_BASEADDR	0xFFA80000
+
 #define PS_MODE0	BIT(0)
 #define PS_MODE1	BIT(1)
 #define PS_MODE2	BIT(2)
--- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
+++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
@ -8,16 +8,34 @@

 BL33="u-boot-nodtb.bin"
 [ -z "$BL31" ] && BL31="bl31.bin"
-# Can be also done as ${CROSS_COMPILE}readelf -l bl31.elf | awk '/Entry point/ { print $3 }'
+BL31_ELF="${BL31%.*}.elf"
+[ -f ${BL31_ELF} ] && ATF_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL31_ELF}" | \
+awk '/Entry point/ { print $3 }'`
+
 [ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000"
+ATF_LOAD_ADDR_LOW=`printf 0x%x $((ATF_LOAD_ADDR & 0xffffffff))`
+ATF_LOAD_ADDR_HIGH=`printf 0x%x $((ATF_LOAD_ADDR >> 32))`
+
+[ -z "$BL32" ] && BL32="tee.bin"
+BL32_ELF="${BL32%.*}.elf"
+[ -f ${BL32_ELF} ] && TEE_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL32_ELF}" | \
+awk '/Entry point/ { print $3 }'`
+
+[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0x60000000"
+TEE_LOAD_ADDR_LOW=`printf 0x%x $((TEE_LOAD_ADDR & 0xffffffff))`
+TEE_LOAD_ADDR_HIGH=`printf 0x%x $((TEE_LOAD_ADDR >> 32))`

 if [ -z "$BL33_LOAD_ADDR" ];then
 	BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }' include/generated/autoconf.h`
 fi
+BL33_LOAD_ADDR_LOW=`printf 0x%x $((BL33_LOAD_ADDR & 0xffffffff))`
+BL33_LOAD_ADDR_HIGH=`printf 0x%x $((BL33_LOAD_ADDR >> 32))`

 DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h`
 if [ ! -z "$DTB_LOAD_ADDR" ]; then
-	DTB_LOAD="load = <$DTB_LOAD_ADDR>;"
+	DTB_LOAD_ADDR_LOW=`printf 0x%x $((DTB_LOAD_ADDR & 0xffffffff))`
+	DTB_LOAD_ADDR_HIGH=`printf 0x%x $((DTB_LOAD_ADDR >> 32))`
+	DTB_LOAD="load = <$DTB_LOAD_ADDR_HIGH $DTB_LOAD_ADDR_LOW>;"
 else
 	DTB_LOAD=""
 fi
@ -49,8 +67,8 @@ cat << __HEADER_EOF
 			os = "u-boot";
 			arch = "arm64";
 			compression = "none";
-			load = <$BL33_LOAD_ADDR>;
-			entry = <$BL33_LOAD_ADDR>;
+			load = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>;
+			entry = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>;
 			hash {
 				algo = "md5";
 			};
@ -66,8 +84,8 @@ cat << __ATF
 			os = "arm-trusted-firmware";
 			arch = "arm64";
 			compression = "none";
-			load = <$ATF_LOAD_ADDR>;
-			entry = <$ATF_LOAD_ADDR>;
+			load = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>;
+			entry = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>;
 			hash {
 				algo = "md5";
 			};
@ -75,6 +93,24 @@ cat << __ATF
 __ATF
 fi

+if [ -f $BL32 ]; then
+cat << __TEE
+		tee {
+			description = "TEE firmware";
+			data = /incbin/("$BL32");
+			type = "firmware";
+			os = "tee";
+			arch = "arm64";
+			compression = "none";
+			load = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>;
+			entry = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>;
+			hash {
+				algo = "md5";
+			};
+		};
+__TEE
+fi
+
 DEFAULT=1
 cnt=1
 for dtname in $DT
@ -117,6 +153,16 @@ cat << __CONF_SECTION1_EOF
 		};
 __CONF_SECTION1_EOF
 else
+if [ -f $BL32 ]; then
+cat << __CONF_SECTION1_EOF
+		config_$cnt {
+			description = "$(basename $dtname .dtb)";
+			firmware = "atf";
+			loadables = "uboot", "tee";
+			fdt = "fdt_$cnt";
+		};
+__CONF_SECTION1_EOF
+else
 cat << __CONF_SECTION1_EOF
 		config_$cnt {
 			description = "$(basename $dtname .dtb)";
@ -126,6 +172,7 @@ cat << __CONF_SECTION1_EOF
 		};
 __CONF_SECTION1_EOF
 fi
+fi

 cnt=$((cnt+1))
 done
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@ -37,6 +37,8 @@

 #define ZYNQMP_CORE_APU0	0
 #define ZYNQMP_CORE_APU3	3
+#define ZYNQMP_CORE_RPU0	4
+#define ZYNQMP_CORE_RPU1	5

 #define ZYNQMP_MAX_CORES	6

@ -54,18 +56,20 @@ int cpu_reset(u32 nr)
 	return 0;
 }

-static void set_r5_halt_mode(u8 halt, u8 mode)
+static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
 {
 	u32 tmp;

-	tmp = readl(&rpu_base->rpu0_cfg);
-	if (halt == HALT)
-		tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
-	else
-		tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
-	writel(tmp, &rpu_base->rpu0_cfg);
+	if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
+		tmp = readl(&rpu_base->rpu0_cfg);
+		if (halt == HALT)
+			tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
+		else
+			tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
+		writel(tmp, &rpu_base->rpu0_cfg);
+	}

-	if (mode == LOCK) {
+	if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
 		tmp = readl(&rpu_base->rpu1_cfg);
 		if (halt == HALT)
 			tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
@ -93,30 +97,34 @@ static void set_r5_tcm_mode(u8 mode)
 	writel(tmp, &rpu_base->rpu_glbl_ctrl);
 }

-static void set_r5_reset(u8 mode)
+static void set_r5_reset(u32 nr, u8 mode)
 {
 	u32 tmp;

 	tmp = readl(&crlapb_base->rst_lpd_top);
-	tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
-	       ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
+	if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
+		tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
+			ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);

-	if (mode == LOCK)
-		tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
+	if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
+		tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
+			ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);

 	writel(tmp, &crlapb_base->rst_lpd_top);
 }

-static void release_r5_reset(u8 mode)
+static void release_r5_reset(u32 nr, u8 mode)
 {
 	u32 tmp;

 	tmp = readl(&crlapb_base->rst_lpd_top);
-	tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
-	       ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
+	if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
+		tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
+			 ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);

-	if (mode == LOCK)
-		tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
+	if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
+		tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
+			 ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);

 	writel(tmp, &crlapb_base->rst_lpd_top);
 }
@ -141,7 +149,7 @@ int cpu_disable(u32 nr)
 		val |= 1 << nr;
 		writel(val, &crfapb_base->rst_fpd_apu);
 	} else {
-		set_r5_reset(LOCK);
+		set_r5_reset(nr, SPLIT);
 	}

 	return 0;
@ -212,14 +220,14 @@ void initialize_tcm(bool mode)
 {
 	if (!mode) {
 		set_r5_tcm_mode(LOCK);
-		set_r5_halt_mode(HALT, LOCK);
+		set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
 		enable_clock_r5();
-		release_r5_reset(LOCK);
+		release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
 	} else {
 		set_r5_tcm_mode(SPLIT);
-		set_r5_halt_mode(HALT, SPLIT);
+		set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
 		enable_clock_r5();
-		release_r5_reset(SPLIT);
+		release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
 	}
 }

@ -268,28 +276,28 @@ int cpu_release(u32 nr, int argc, char *const argv[])

 		if (!strncmp(argv[1], "lockstep", 8)) {
 			printf("R5 lockstep mode\n");
-			set_r5_reset(LOCK);
+			set_r5_reset(nr, LOCK);
 			set_r5_tcm_mode(LOCK);
-			set_r5_halt_mode(HALT, LOCK);
+			set_r5_halt_mode(nr, HALT, LOCK);
 			set_r5_start(boot_addr);
 			enable_clock_r5();
-			release_r5_reset(LOCK);
+			release_r5_reset(nr, LOCK);
 			dcache_disable();
 			write_tcm_boot_trampoline(boot_addr_uniq);
 			dcache_enable();
-			set_r5_halt_mode(RELEASE, LOCK);
+			set_r5_halt_mode(nr, RELEASE, LOCK);
 		} else if (!strncmp(argv[1], "split", 5)) {
 			printf("R5 split mode\n");
-			set_r5_reset(SPLIT);
+			set_r5_reset(nr, SPLIT);
 			set_r5_tcm_mode(SPLIT);
-			set_r5_halt_mode(HALT, SPLIT);
+			set_r5_halt_mode(nr, HALT, SPLIT);
 			set_r5_start(boot_addr);
 			enable_clock_r5();
-			release_r5_reset(SPLIT);
+			release_r5_reset(nr, SPLIT);
 			dcache_disable();
 			write_tcm_boot_trampoline(boot_addr_uniq);
 			dcache_enable();
-			set_r5_halt_mode(RELEASE, SPLIT);
+			set_r5_halt_mode(nr, RELEASE, SPLIT);
 		} else {
 			printf("Unsupported mode\n");
 			return 1;
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@ -15,6 +15,7 @@
 #include <asm/io.h>
 #include <asm/spl.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/ecc_spl_init.h>
 #include <asm/arch/psu_init_gpl.h>
 #include <asm/arch/sys_proto.h>

@ -22,6 +23,9 @@ void board_init_f(ulong dummy)
 {
 	board_early_init_f();
 	board_early_init_r();
+#ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT
+	zynqmp_ecc_init();
+#endif
 }

 static void ps_mode_reset(ulong mode)
--- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
@ -0,0 +1,673 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07340301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102411U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A09U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07221008U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00311008U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000634U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xD4000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0357FFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0001007EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x02841284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000006U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000007CU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0004U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0000U);
+	mask_delay(5);
+	psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0004U);
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+	int cur_r006_trefprd;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+
+	cur_r006_trefprd = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_r006_trefprd);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_r006_trefprd);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
--- a/board/xilinx/zynqmp/zynqmp-smk-k26-revA
+++ b/board/xilinx/zynqmp/zynqmp-smk-k26-revA
@ -0,0 +1 @@
+zynqmp-sm-k26-revA
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@ -11,6 +11,8 @@
 #include <env.h>
 #include <env_internal.h>
 #include <init.h>
+#include <image.h>
+#include <lmb.h>
 #include <log.h>
 #include <net.h>
 #include <sata.h>
@ -183,8 +185,39 @@ static const struct {
 		.device = 49,
 		.variants = ZYNQMP_VARIANT_DR,
 	},
+	{
+		.id = 0x046d0093,
+		.device = 67,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
 };

+static const struct {
+	u32 id;
+	char *name;
+} zynqmp_svd_devices[] = {
+	{
+		.id = 0x04714093,
+		.name = "xck24"
+	},
+	{
+		.id = 0x04724093,
+		.name = "xck26",
+	},
+};
+
+static char *zynqmp_detect_svd_name(u32 idcode)
+{
+	u32 i;
+
+	for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) {
+		if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF))
+			return zynqmp_svd_devices[i].name;
+	}
+
+	return "unknown";
+}
+
 static char *zynqmp_get_silicon_idcode_name(void)
 {
 	u32 i;
@ -219,7 +252,7 @@ static char *zynqmp_get_silicon_idcode_name(void)
 	}

 	if (i >= ARRAY_SIZE(zynqmp_devices))
-		return "unknown";
+		return zynqmp_detect_svd_name(idcode);

 	/* Add device prefix to the name */
 	ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
@ -427,6 +460,25 @@ int dram_init(void)

 	return 0;
 }
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	phys_size_t size;
+	phys_addr_t reg;
+	struct lmb lmb;
+
+	/* found enough not-reserved memory to relocated U-Boot */
+	lmb_init(&lmb);
+	lmb_add(&lmb, gd->ram_base, gd->ram_size);
+	boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
+	size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
+	reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
+
+	if (!reg)
+		reg = gd->ram_top - size;
+
+	return reg + size;
+}
 #else
 int dram_init_banksize(void)
 {
@ -694,6 +746,41 @@ int checkboard(void)
 	return 0;
 }

+int mmc_get_env_dev(void)
+{
+	struct udevice *dev;
+	int bootseq = 0;
+
+	switch (zynqmp_get_bootmode()) {
+	case EMMC_MODE:
+	case SD_MODE:
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff160000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff160000", &dev)) {
+			return -1;
+		}
+		bootseq = dev_seq(dev);
+		break;
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff170000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff170000", &dev)) {
+			return -1;
+		}
+		bootseq = dev_seq(dev);
+		break;
+	default:
+		break;
+	}
+
+	debug("bootseq %d\n", bootseq);
+
+	return bootseq;
+}
+
 enum env_location env_get_location(enum env_operation op, int prio)
 {
 	u32 bootmode = zynqmp_get_bootmode();
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@ -594,7 +594,7 @@ void fdt_fixup_ethernet(void *fdt)

 int fdt_record_loadable(void *blob, u32 index, const char *name,
 			uintptr_t load_addr, u32 size, uintptr_t entry_point,
-			const char *type, const char *os)
+			const char *type, const char *os, const char *arch)
 {
 	int err, node;

@ -622,6 +622,8 @@ int fdt_record_loadable(void *blob, u32 index, const char *name,
 		fdt_setprop_string(blob, node, "type", type);
 	if (os)
 		fdt_setprop_string(blob, node, "os", os);
+	if (arch)
+		fdt_setprop_string(blob, node, "arch", arch);

 	return node;
 }
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@ -480,7 +480,8 @@ static int spl_fit_record_loadable(const struct spl_fit_info *ctx, int index,
 	ret = fdt_record_loadable(blob, index, name, image->load_addr,
 				  image->size, image->entry_point,
 				  fdt_getprop(ctx->fit, node, "type", NULL),
-				  fdt_getprop(ctx->fit, node, "os", NULL));
+				  fdt_getprop(ctx->fit, node, "os", NULL),
+				  fdt_getprop(ctx->fit, node, "arch", NULL));
 	return ret;
 }

--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_ZYNQMP_FIRMWARE=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_ARM_DCC=y
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_ZYNQMP_FIRMWARE=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_ARM_DCC=y
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQMP_FIRMWARE=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQMP_FIRMWARE=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@ -54,6 +54,7 @@ CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
@ -61,6 +62,7 @@ CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_GETTIME=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
@ -76,6 +78,7 @@ CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART=":auto"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
@ -142,6 +145,8 @@ CONFIG_PHY_XILINX_GMII2RGMII=y
 CONFIG_PHY_FIXED=y
 CONFIG_XILINX_AXIEMAC=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
 CONFIG_SCSI=y
@ -190,3 +195,4 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@ -128,6 +128,17 @@ config CLK_ZYNQ
 	  This clock driver adds support for clock related settings for
 	  Zynq platform.

+config CLK_XLNX_CLKWZRD
+	bool "Xilinx Clocking Wizard"
+	depends on CLK
+	help
+	  Support for the Xilinx Clocking Wizard IP core clock generator.
+	  The wizard support for dynamically reconfiguring the clocking
+	  primitives for Multiply, Divide, Phase Shift/Offset, or Duty
+	  Cycle. Limited by U-Boot clk uclass without set_phase API and
+	  set_duty_cycle API, this driver only supports set_rate to modify
+	  the frequency.
+
 config CLK_ZYNQMP
 	bool "Enable clock driver support for ZynqMP"
 	depends on ARCH_ZYNQMP
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
 obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
 obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
+obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
 obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx 'Clocking Wizard' driver
+ *
+ * Copyright (c) 2021 Macronix Inc.
+ *
+ * Author: Zhengxun Li <zhengxunli@mxic.com.tw>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <div64.h>
+#include <dm/device_compat.h>
+#include <linux/iopoll.h>
+
+#include <linux/bitfield.h>
+
+#define SRR			0x0
+
+#define SR			0x4
+#define SR_LOCKED		BIT(0)
+
+#define CCR(x)			(0x200 + ((x) * 4))
+
+#define FBOUT_CFG		CCR(0)
+#define FBOUT_DIV(x)		(x)
+#define FBOUT_DIV_MASK		GENMASK(7, 0)
+#define FBOUT_GET_DIV(x)	FIELD_GET(FBOUT_DIV_MASK, x)
+#define FBOUT_MUL(x)		((x) << 8)
+#define FBOUT_MUL_MASK		GENMASK(15, 8)
+#define FBOUT_GET_MUL(x)	FIELD_GET(FBOUT_MUL_MASK, x)
+#define FBOUT_FRAC(x)		((x) << 16)
+#define FBOUT_FRAC_MASK		GENMASK(25, 16)
+#define FBOUT_GET_FRAC(x)	FIELD_GET(FBOUT_FRAC_MASK, x)
+#define FBOUT_FRAC_EN		BIT(26)
+
+#define FBOUT_PHASE		CCR(1)
+
+#define OUT_CFG(x)		CCR(2 + ((x) * 3))
+#define OUT_DIV(x)		(x)
+#define OUT_DIV_MASK		GENMASK(7, 0)
+#define OUT_GET_DIV(x)		FIELD_GET(OUT_DIV_MASK, x)
+#define OUT_FRAC(x)		((x) << 8)
+#define OUT_GET_MASK		GENMASK(17, 8)
+#define OUT_GET_FRAC(x)		FIELD_GET(OUT_GET_MASK, x)
+#define OUT_FRAC_EN		BIT(18)
+
+#define OUT_PHASE(x)		CCR(3 + ((x) * 3))
+#define OUT_DUTY(x)		CCR(4 + ((x) * 3))
+
+#define CTRL			CCR(23)
+#define CTRL_SEN		BIT(2)
+#define CTRL_SADDR		BIT(1)
+#define CTRL_LOAD		BIT(0)
+
+/**
+ * struct clkwzrd - Clock wizard private data structure
+ *
+ * @base:		memory base
+ * @vco_clk:		voltage-controlled oscillator frequency
+ *
+ */
+struct clkwzd {
+	void *base;
+	u64 vco_clk;
+};
+
+struct clkwzd_plat {
+	fdt_addr_t addr;
+};
+
+static int clk_wzrd_enable(struct clk *clk)
+{
+	struct clkwzd *priv = dev_get_priv(clk->dev);
+	int ret;
+	u32 val;
+
+	ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED,
+				       1, 100);
+	if (!ret) {
+		writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL);
+		writel(CTRL_SADDR, priv->base + CTRL);
+		ret = readl_poll_sleep_timeout(priv->base + SR, val,
+					       val & SR_LOCKED, 1, 100);
+	}
+
+	return ret;
+}
+
+static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)
+{
+	struct clkwzd *priv = dev_get_priv(clk->dev);
+	u64 div;
+	u32 cfg;
+
+	/* Get output clock divide value */
+	div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate);
+	if (div < 1000 || div > 255999)
+		return -EINVAL;
+
+	cfg = OUT_DIV((u32)div / 1000);
+
+	writel(cfg, priv->base + OUT_CFG(clk->id));
+
+	return 0;
+}
+
+static struct clk_ops clk_wzrd_ops = {
+	.enable = clk_wzrd_enable,
+	.set_rate = clk_wzrd_set_rate,
+};
+
+static int clk_wzrd_probe(struct udevice *dev)
+{
+	struct clkwzd_plat *plat = dev_get_plat(dev);
+	struct clkwzd *priv = dev_get_priv(dev);
+	struct clk clk_in1;
+	u64 clock, vco_clk;
+	u32 cfg;
+	int ret;
+
+	priv->base = (void *)plat->addr;
+
+	ret = clk_get_by_name(dev, "clk_in1", &clk_in1);
+	if (ret < 0) {
+		dev_err(dev, "failed to get clock\n");
+		return ret;
+	}
+
+	clock = clk_get_rate(&clk_in1);
+	if (IS_ERR_VALUE(clock)) {
+		dev_err(dev, "failed to get rate\n");
+		return clock;
+	}
+
+	ret = clk_enable(&clk_in1);
+	if (ret) {
+		dev_err(dev, "failed to enable clock\n");
+		clk_free(&clk_in1);
+		return ret;
+	}
+
+	/* Read clock configuration registers */
+	cfg = readl(priv->base + FBOUT_CFG);
+
+	/* Recalculate VCO rate */
+	if (cfg & FBOUT_FRAC_EN)
+		vco_clk = DIV_ROUND_DOWN_ULL(clock *
+					     ((FBOUT_GET_MUL(cfg) * 1000) +
+					      FBOUT_GET_FRAC(cfg)),
+					     1000);
+	else
+		vco_clk = clock * FBOUT_GET_MUL(cfg);
+
+	priv->vco_clk = DIV_ROUND_DOWN_ULL(vco_clk, FBOUT_GET_DIV(cfg));
+
+	return 0;
+}
+
+static int clk_wzrd_of_to_plat(struct udevice *dev)
+{
+	struct clkwzd_plat *plat = dev_get_plat(dev);
+
+	plat->addr = dev_read_addr(dev);
+	if (plat->addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct udevice_id clk_wzrd_ids[] = {
+	{ .compatible = "xlnx,clocking-wizard" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_wzrd) = {
+	.name = "zynq-clk-wizard",
+	.id = UCLASS_CLK,
+	.of_match = clk_wzrd_ids,
+	.ops = &clk_wzrd_ops,
+	.probe = clk_wzrd_probe,
+	.of_to_plat = clk_wzrd_of_to_plat,
+	.priv_auto = sizeof(struct clkwzd),
+	.plat_auto = sizeof(struct clkwzd_plat),
+};
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@ -396,7 +396,7 @@ config DM_74X164

 config DM_PCA953X
 	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
-	depends on DM_GPIO
+	depends on DM_GPIO && DM_I2C
 	help
 	  Say yes here to provide access to several register-oriented
 	  SMBus I/O expanders, made mostly by NXP or TI.  Compatible
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (C) 2021 Waymo LLC
 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2011 PetaLogix
 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
@ -73,9 +74,22 @@ DECLARE_GLOBAL_DATA_PTR;
 #define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /* First tx packet */
 #define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /* Last tx packet */

-#define DMAALIGN	128
+/* Bitmasks for XXV Ethernet MAC */
+#define XXV_TC_TX_MASK		0x00000001
+#define XXV_TC_FCS_MASK		0x00000002
+#define XXV_RCW1_RX_MASK	0x00000001
+#define XXV_RCW1_FCS_MASK	0x00000002
+
+#define DMAALIGN		128
+#define XXV_MIN_PKT_SIZE	60

 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
+static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
+
+enum emac_variant {
+	EMAC_1G = 0,
+	EMAC_10G_25G = 1,
+};

 /* Reflect dma offsets */
 struct axidma_reg {
@ -87,6 +101,17 @@ struct axidma_reg {
 	u32 tail_hi; /* TAILDESC high 32 bit */
 };

+/* Platform data structures */
+struct axidma_plat {
+	struct eth_pdata eth_pdata;
+	struct axidma_reg *dmatx;
+	struct axidma_reg *dmarx;
+	int phyaddr;
+	u8 eth_hasnobuf;
+	int phy_of_handle;
+	enum emac_variant mactype;
+};
+
 /* Private driver structures */
 struct axidma_priv {
 	struct axidma_reg *dmatx;
@ -98,6 +123,7 @@ struct axidma_priv {
 	struct mii_dev *bus;
 	u8 eth_hasnobuf;
 	int phy_of_handle;
+	enum emac_variant mactype;
 };

 /* BD descriptors */
@ -144,6 +170,14 @@ struct axi_regs {
 	u32 uaw1; /* 0x704: Unicast address word 1 */
 };

+struct xxv_axi_regs {
+	u32 gt_reset;	/* 0x0 */
+	u32 reserved[2];
+	u32 tc;		/* 0xC: Tx Configuration */
+	u32 reserved2;
+	u32 rcw1;	/* 0x14: Rx Configuration Word 1 */
+};
+
 /* Use MII register 1 (MII status register) to detect PHY */
 #define PHY_DETECT_REG  1

@ -375,6 +409,18 @@ static void axiemac_stop(struct udevice *dev)
 	debug("axiemac: Halted\n");
 }

+static int xxv_axi_ethernet_init(struct axidma_priv *priv)
+{
+	struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
+
+	writel(readl(&regs->rcw1) | XXV_RCW1_FCS_MASK, &regs->rcw1);
+	writel(readl(&regs->tc) | XXV_TC_FCS_MASK, &regs->tc);
+	writel(readl(&regs->tc) | XXV_TC_TX_MASK, &regs->tc);
+	writel(readl(&regs->rcw1) | XXV_RCW1_RX_MASK, &regs->rcw1);
+
+	return 0;
+}
+
 static int axi_ethernet_init(struct axidma_priv *priv)
 {
 	struct axi_regs *regs = priv->iobase;
@ -430,6 +476,9 @@ static int axiemac_write_hwaddr(struct udevice *dev)
 	struct axidma_priv *priv = dev_get_priv(dev);
 	struct axi_regs *regs = priv->iobase;

+	if (priv->mactype != EMAC_1G)
+		return 0;
+
 	/* Set the MAC address */
 	int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
 		(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
@ -467,7 +516,6 @@ static void axi_dma_init(struct axidma_priv *priv)
 static int axiemac_start(struct udevice *dev)
 {
 	struct axidma_priv *priv = dev_get_priv(dev);
-	struct axi_regs *regs = priv->iobase;
 	u32 temp;

 	debug("axiemac: Init started\n");
@ -480,8 +528,13 @@ static int axiemac_start(struct udevice *dev)
 	axi_dma_init(priv);

 	/* Initialize AxiEthernet hardware. */
-	if (axi_ethernet_init(priv))
-		return -1;
+	if (priv->mactype == EMAC_1G) {
+		if (axi_ethernet_init(priv))
+			return -1;
+	} else {
+		if (xxv_axi_ethernet_init(priv))
+			return -1;
+	}

 	/* Disable all RX interrupts before RxBD space setup */
 	temp = readl(&priv->dmarx->control);
@ -515,15 +568,25 @@ static int axiemac_start(struct udevice *dev)
 	/* Rx BD is ready - start */
 	axienet_dma_write(&rx_bd, &priv->dmarx->tail);

-	/* Enable TX */
-	writel(XAE_TC_TX_MASK, &regs->tc);
-	/* Enable RX */
-	writel(XAE_RCW1_RX_MASK, &regs->rcw1);
+	if (priv->mactype == EMAC_1G) {
+		struct axi_regs *regs = priv->iobase;
+		/* Enable TX */
+		writel(XAE_TC_TX_MASK, &regs->tc);
+		/* Enable RX */
+		writel(XAE_RCW1_RX_MASK, &regs->rcw1);

-	/* PHY setup */
-	if (!setup_phy(dev)) {
-		axiemac_stop(dev);
-		return -1;
+		/* PHY setup */
+		if (!setup_phy(dev)) {
+			axiemac_stop(dev);
+			return -1;
+		}
+	} else {
+		struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
+		/* Enable TX */
+		writel(readl(&regs->tc) | XXV_TC_TX_MASK, &regs->tc);
+
+		/* Enable RX */
+		writel(readl(&regs->rcw1) | XXV_RCW1_RX_MASK, &regs->rcw1);
 	}

 	debug("axiemac: Init complete\n");
@ -538,6 +601,14 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
 	if (len > PKTSIZE_ALIGN)
 		len = PKTSIZE_ALIGN;

+	/* If size is less than min packet size, pad to min size */
+	if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) {
+		memset(txminframe, 0, XXV_MIN_PKT_SIZE);
+		memcpy(txminframe, ptr, len);
+		len = XXV_MIN_PKT_SIZE;
+		ptr = txminframe;
+	}
+
 	/* Flush packet to main memory to be trasfered by DMA */
 	flush_cache((phys_addr_t)ptr, len);

@ -622,7 +693,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
 	temp = readl(&priv->dmarx->control);
 	temp &= ~XAXIDMA_IRQ_ALL_MASK;
 	writel(temp, &priv->dmarx->control);
-	if (!priv->eth_hasnobuf)
+	if (!priv->eth_hasnobuf  && priv->mactype == EMAC_1G)
 		length = rx_bd.app4 & 0xFFFF; /* max length mask */
 	else
 		length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
@ -690,19 +761,34 @@ static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,

 static int axi_emac_probe(struct udevice *dev)
 {
+	struct axidma_plat *plat = dev_get_plat(dev);
+	struct eth_pdata *pdata = &plat->eth_pdata;
 	struct axidma_priv *priv = dev_get_priv(dev);
 	int ret;

-	priv->bus = mdio_alloc();
-	priv->bus->read = axiemac_miiphy_read;
-	priv->bus->write = axiemac_miiphy_write;
-	priv->bus->priv = priv;
+	priv->iobase = (struct axi_regs *)pdata->iobase;
+	priv->dmatx = plat->dmatx;
+	/* RX channel offset is 0x30 */
+	priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
+	priv->mactype = plat->mactype;

-	ret = mdio_register_seq(priv->bus, dev_seq(dev));
-	if (ret)
-		return ret;
+	if (priv->mactype == EMAC_1G) {
+		priv->eth_hasnobuf = plat->eth_hasnobuf;
+		priv->phyaddr = plat->phyaddr;
+		priv->phy_of_handle = plat->phy_of_handle;
+		priv->interface = pdata->phy_interface;

-	axiemac_phy_init(dev);
+		priv->bus = mdio_alloc();
+		priv->bus->read = axiemac_miiphy_read;
+		priv->bus->write = axiemac_miiphy_write;
+		priv->bus->priv = priv;
+
+		ret = mdio_register_seq(priv->bus, dev_seq(dev));
+		if (ret)
+			return ret;
+
+		axiemac_phy_init(dev);
+	}

 	return 0;
 }
@ -711,9 +797,11 @@ static int axi_emac_remove(struct udevice *dev)
 {
 	struct axidma_priv *priv = dev_get_priv(dev);

-	free(priv->phydev);
-	mdio_unregister(priv->bus);
-	mdio_free(priv->bus);
+	if (priv->mactype == EMAC_1G) {
+		free(priv->phydev);
+		mdio_unregister(priv->bus);
+		mdio_free(priv->bus);
+	}

 	return 0;
 }
@ -729,14 +817,14 @@ static const struct eth_ops axi_emac_ops = {

 static int axi_emac_of_to_plat(struct udevice *dev)
 {
-	struct eth_pdata *pdata = dev_get_plat(dev);
-	struct axidma_priv *priv = dev_get_priv(dev);
+	struct axidma_plat *plat = dev_get_plat(dev);
+	struct eth_pdata *pdata = &plat->eth_pdata;
 	int node = dev_of_offset(dev);
 	int offset = 0;
 	const char *phy_mode;

 	pdata->iobase = dev_read_addr(dev);
-	priv->iobase = (struct axi_regs *)pdata->iobase;
+	plat->mactype = dev_get_driver_data(dev);

 	offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
 				       "axistream-connected");
@ -744,43 +832,46 @@ static int axi_emac_of_to_plat(struct udevice *dev)
 		printf("%s: axistream is not found\n", __func__);
 		return -EINVAL;
 	}
-	priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
+	plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
 							  offset, "reg");
-	if (!priv->dmatx) {
+	if (!plat->dmatx) {
 		printf("%s: axi_dma register space not found\n", __func__);
 		return -EINVAL;
 	}
-	/* RX channel offset is 0x30 */
-	priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);

-	priv->phyaddr = -1;
+	if (plat->mactype == EMAC_1G) {
+		plat->phyaddr = -1;

-	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
-	if (offset > 0) {
-		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
-		priv->phy_of_handle = offset;
+		offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
+					       "phy-handle");
+		if (offset > 0) {
+			plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
+						       "reg", -1);
+			plat->phy_of_handle = offset;
+		}
+
+		phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
+		if (phy_mode)
+			pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+		if (pdata->phy_interface == -1) {
+			printf("%s: Invalid PHY interface '%s'\n", __func__,
+			       phy_mode);
+			return -EINVAL;
+		}
+
+		plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
+						     "xlnx,eth-hasnobuf");
 	}

-	phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
-	if (phy_mode)
-		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
-	if (pdata->phy_interface == -1) {
-		printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
-		return -EINVAL;
-	}
-	priv->interface = pdata->phy_interface;
-
-	priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
-					     "xlnx,eth-hasnobuf");
-
-	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
-	       priv->phyaddr, phy_string_for_interface(priv->interface));
+	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
+	       plat->phyaddr, phy_string_for_interface(pdata->phy_interface));

 	return 0;
 }

 static const struct udevice_id axi_emac_ids[] = {
-	{ .compatible = "xlnx,axi-ethernet-1.00.a" },
+	{ .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G },
+	{ .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G },
 	{ }
 };

@ -793,5 +884,5 @@ U_BOOT_DRIVER(axi_emac) = {
 	.remove	= axi_emac_remove,
 	.ops	= &axi_emac_ops,
 	.priv_auto	= sizeof(struct axidma_priv),
-	.plat_auto	= sizeof(struct eth_pdata),
+	.plat_auto	= sizeof(struct axidma_plat),
 };
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@ -332,7 +332,7 @@ config DEBUG_UART_APBUART

 config DEBUG_UART_PL010
 	bool "pl010"
-	depends on PL01X_SERIAL
+	depends on PL01X_SERIAL || PL010_SERIAL
 	help
 	  Select this to enable a debug UART using the pl01x driver with the
 	  PL010 UART type. You will need to provide parameters to make this
@ -341,7 +341,7 @@ config DEBUG_UART_PL010

 config DEBUG_UART_PL011
 	bool "pl011"
-	depends on PL011_SERIAL
+	depends on PL01X_SERIAL || PL011_SERIAL
 	help
 	  Select this to enable a debug UART using the pl01x driver with the
 	  PL011 UART type. You will need to provide parameters to make this
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@ -28,7 +28,17 @@
 #define ZYNQ_UART_CR_TXRST	BIT(1) /* TX logic reset */
 #define ZYNQ_UART_CR_RXRST	BIT(0) /* RX logic reset */

+#define ZYNQ_UART_MR_STOPMODE_2_BIT	0x00000080  /* 2 stop bits */
+#define ZYNQ_UART_MR_STOPMODE_1_5_BIT	0x00000040  /* 1.5 stop bits */
+#define ZYNQ_UART_MR_STOPMODE_1_BIT	0x00000000  /* 1 stop bit */
+
 #define ZYNQ_UART_MR_PARITY_NONE	0x00000020  /* No parity mode */
+#define ZYNQ_UART_MR_PARITY_ODD		0x00000008  /* Odd parity mode */
+#define ZYNQ_UART_MR_PARITY_EVEN	0x00000000  /* Even parity mode */
+
+#define ZYNQ_UART_MR_CHARLEN_6_BIT	0x00000006  /* 6 bits data */
+#define ZYNQ_UART_MR_CHARLEN_7_BIT	0x00000004  /* 7 bits data */
+#define ZYNQ_UART_MR_CHARLEN_8_BIT	0x00000000  /* 8 bits data */

 struct uart_zynq {
 	u32 control; /* 0x0 - Control Register [8:0] */
@ -137,6 +147,63 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
 	return 0;
 }

+#if !defined(CONFIG_SPL_BUILD)
+static int zynq_serial_setconfig(struct udevice *dev, uint serial_config)
+{
+	struct zynq_uart_plat *plat = dev_get_plat(dev);
+	struct uart_zynq *regs = plat->regs;
+	u32 val = 0;
+
+	switch (SERIAL_GET_BITS(serial_config)) {
+	case SERIAL_6_BITS:
+		val |= ZYNQ_UART_MR_CHARLEN_6_BIT;
+		break;
+	case SERIAL_7_BITS:
+		val |= ZYNQ_UART_MR_CHARLEN_7_BIT;
+		break;
+	case SERIAL_8_BITS:
+		val |= ZYNQ_UART_MR_CHARLEN_8_BIT;
+		break;
+	default:
+		return -ENOTSUPP; /* not supported in driver */
+	}
+
+	switch (SERIAL_GET_STOP(serial_config)) {
+	case SERIAL_ONE_STOP:
+		val |= ZYNQ_UART_MR_STOPMODE_1_BIT;
+		break;
+	case SERIAL_ONE_HALF_STOP:
+		val |= ZYNQ_UART_MR_STOPMODE_1_5_BIT;
+		break;
+	case SERIAL_TWO_STOP:
+		val |= ZYNQ_UART_MR_STOPMODE_2_BIT;
+		break;
+	default:
+		return -ENOTSUPP; /* not supported in driver */
+	}
+
+	switch (SERIAL_GET_PARITY(serial_config)) {
+	case SERIAL_PAR_NONE:
+		val |= ZYNQ_UART_MR_PARITY_NONE;
+		break;
+	case SERIAL_PAR_ODD:
+		val |= ZYNQ_UART_MR_PARITY_ODD;
+		break;
+	case SERIAL_PAR_EVEN:
+		val |= ZYNQ_UART_MR_PARITY_EVEN;
+		break;
+	default:
+		return -ENOTSUPP; /* not supported in driver */
+	}
+
+	writel(val, &regs->mode);
+
+	return 0;
+}
+#else
+#define zynq_serial_setconfig NULL
+#endif
+
 static int zynq_serial_probe(struct udevice *dev)
 {
 	struct zynq_uart_plat *plat = dev_get_plat(dev);
@ -198,6 +265,7 @@ static const struct dm_serial_ops zynq_serial_ops = {
 	.pending = zynq_serial_pending,
 	.getc = zynq_serial_getc,
 	.setbrg = zynq_serial_setbrg,
+	.setconfig = zynq_serial_setconfig,
 };

 static const struct udevice_id zynq_serial_ids[] = {
--- a/drivers/watchdog/cdns_wdt.c
+++ b/drivers/watchdog/cdns_wdt.c
@ -214,6 +214,45 @@ static int cdns_wdt_stop(struct udevice *dev)
 	return 0;
 }

+/**
+ * cdns_wdt_expire_now - Expire the watchdog.
+ *
+ * @dev: Watchdog device
+ * @flags: Driver flags
+ *
+ * Access WDT and configure with minimal counter value to expire ASAP.
+ * Expiration issues system reset. When DEBUG is enabled count should be
+ * bigger to at least see debug message.
+ *
+ * Return: Always 0
+ */
+static int cdns_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+	struct cdns_wdt_priv *priv = dev_get_priv(dev);
+	u32 data, count = 0;
+
+#if defined(DEBUG)
+	count = 0x40; /* Increase the value if you need more time */
+	debug("%s: Expire wdt%u\n", __func__, dev_seq(dev));
+#endif
+
+	cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL);
+
+	count = (count << 2) & CDNS_WDT_CCR_CRV_MASK;
+
+	/* Write counter access key first to be able write to register */
+	data = count | CDNS_WDT_REGISTER_ACCESS_KEY;
+	cdns_wdt_writereg(&priv->regs->ccr, data);
+
+	data = CDNS_WDT_ZMR_WDEN_MASK |  CDNS_WDT_ZMR_RSTEN_MASK |
+		CDNS_WDT_ZMR_ZKEY_VAL;
+
+	cdns_wdt_writereg(&priv->regs->zmr, data);
+	cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
+
+	return 0;
+}
+
 /**
 * cdns_wdt_probe - Probe call for the device.
 *
@ -247,7 +286,7 @@ static const struct wdt_ops cdns_wdt_ops = {
 	.start = cdns_wdt_start,
 	.reset = cdns_wdt_reset,
 	.stop = cdns_wdt_stop,
-	/* There is no bit/reg/support in IP for expire_now functionality */
+	.expire_now = cdns_wdt_expire_now,
 };

 static const struct udevice_id cdns_wdt_ids[] = {
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@ -160,11 +160,12 @@ static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
 * @param entry_point   entry point (if specified, otherwise pass -1)
 * @param type          type (if specified, otherwise pass NULL)
 * @param os            os-type (if specified, otherwise pass NULL)
+ * @param arch		architecture (if specified, otherwise pass NULL)
 * @return 0 if ok, or -1 or -FDT_ERR_... on error
 */
 int fdt_record_loadable(void *blob, u32 index, const char *name,
 			uintptr_t load_addr, u32 size, uintptr_t entry_point,
-			const char *type, const char *os);
+			const char *type, const char *os, const char *arch);

 #ifdef CONFIG_PCI
 #include <pci.h>