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83xx: Remove warmboot parameter from PCI init functions

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This change lays the groundwork for the BOOTFLAG_* flags being removed.

This change has the small affect of delaying 100ms on PCI initialization
after a warm boot as opposed to the optimal 1ms on some boards.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

included the mpc8308_p1m board.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Peter Tyser 2010-09-14 19:13:50 -05:00 committed by Wolfgang Denk
parent 9eda770b46
commit 6aa3d3bfaa
21 changed files with 35 additions and 54 deletions
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6
arch/powerpc/cpu/mpc83xx/pci.c
View File

@ -133,7 +133,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
* If fewer than three regions are requested, then the region
* list is terminated with a region of size 0.
*/
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
int i;
@ -150,9 +150,9 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
/*
* Release PCI RST Output signal.
* Power on to RST high must be at least 100 ms as per PCI spec.
* On warm boots only 1 ms is required.
* On warm boots only 1 ms is required, but we play it safe.
*/
udelay(warmboot ? 1000 : 100000);
udelay(100000);
for (i = 0; i < num_buses; i++)
immr->pci_ctrl[i].gcr = 1;

6
arch/powerpc/cpu/mpc83xx/pcie.c
View File

@ -308,16 +308,16 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
* The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
* must have been set to cover all of the requested regions.
*/
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot)
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
{
int i;
/*
* Release PCI RST Output signal.
* Power on to RST high must be at least 100 ms as per PCI spec.
* On warm boots only 1 ms is required.
* On warm boots only 1 ms is required, but we play it safe.
*/
udelay(warmboot ? 1000 : 100000);
udelay(100000);
if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
printf("Second PCIE host contoller not configured!\n");

2
board/esd/vme8349/pci.c
View File

@ -124,7 +124,7 @@ pci_init_board(void)
udelay(2000);
if (monarch == 0) {
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
} else {
/*
* Release PCI RST Output signal

2
board/freescale/mpc8308rdb/mpc8308rdb.c
View File

@ -100,7 +100,7 @@ void pci_init_board(void)
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(1, pcie_reg, 0);
mpc83xx_pcie_init(1, pcie_reg);
}
/*
* Miscellaneous late-boot configurations

8
board/freescale/mpc8313erdb/mpc8313erdb.c
View File

@ -80,7 +80,6 @@ void pci_init_board(void)
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
@ -94,12 +93,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
#endif
mpc83xx_pci_init(1, reg, warmboot);
mpc83xx_pci_init(1, reg);
}
/*

8
board/freescale/mpc8315erdb/mpc8315erdb.c
View File

@ -140,7 +140,6 @@ void pci_init_board(void)
volatile law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *reg[] = { pci_regions };
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
@ -154,10 +153,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
mpc83xx_pci_init(1, reg, warmboot);
mpc83xx_pci_init(1, reg);
/* Configure the clock for PCIE controller */
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
@ -175,7 +171,7 @@ void pci_init_board(void)
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(2, pcie_reg, warmboot);
mpc83xx_pcie_init(2, pcie_reg);
}
#if defined(CONFIG_OF_BOARD_SETUP)

2
board/freescale/mpc8323erdb/mpc8323erdb.c
View File

@ -173,7 +173,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
}
#if defined(CONFIG_OF_BOARD_SETUP)

6
board/freescale/mpc832xemds/pci.c
View File

@ -86,7 +86,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
/*
* Configure PCI Inbound Translation Windows
@ -147,9 +147,9 @@ void pci_init_board(void)
udelay(2000);
#ifndef CONFIG_MPC83XX_PCI2
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
#else
mpc83xx_pci_init(2, reg, 0);
mpc83xx_pci_init(2, reg);
#endif
}
#endif /* CONFIG_PCISLAVE */

6
board/freescale/mpc8349emds/pci.c
View File

@ -161,9 +161,9 @@ void pci_init_board(void)
udelay(2000);
#ifndef CONFIG_MPC83XX_PCI2
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
#else
mpc83xx_pci_init(2, reg, 0);
mpc83xx_pci_init(2, reg);
#endif
}
@ -182,7 +182,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
/* Configure PCI Inbound Translation Windows (3 1MB windows) */
pci_ctrl->pitar0 = 0x0;

4
board/freescale/mpc8349itx/pci.c
View File

@ -114,8 +114,8 @@ void pci_init_board(void)
udelay(2000);
#ifndef CONFIG_MPC83XX_PCI2
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
#else
mpc83xx_pci_init(2, reg, 0);
mpc83xx_pci_init(2, reg);
#endif
}

6
board/freescale/mpc8360emds/pci.c
View File

@ -84,7 +84,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
/*
* Configure PCI Inbound Translation Windows
@ -145,9 +145,9 @@ void pci_init_board(void)
udelay(2000);
#ifndef CONFIG_MPC83XX_PCI2
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
#else
mpc83xx_pci_init(2, reg, 0);
mpc83xx_pci_init(2, reg);
#endif
}
#endif /* CONFIG_PCISLAVE */

2
board/freescale/mpc8360erdk/mpc8360erdk.c
View File

@ -344,7 +344,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
}
#if defined(CONFIG_OF_BOARD_SETUP)

2
board/freescale/mpc837xemds/pci.c
View File

@ -108,7 +108,7 @@ void pci_init_board(void)
udelay(2000);
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
skip_pci:
/* There is no PEX in MPC8379 parts. */
if (PARTID_NO_E(spridr) == SPR_8379)

4
board/freescale/mpc837xerdb/pci.c
View File

@ -88,7 +88,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
/* There is no PEX in MPC8379 parts. */
if (PARTID_NO_E(spridr) == SPR_8379)
@ -110,5 +110,5 @@ void pci_init_board(void)
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(2, pcie_reg, 0);
mpc83xx_pcie_init(2, pcie_reg);
}

5
board/matrix_vision/mvblm7/pci.c
View File

@ -60,7 +60,6 @@ static struct pci_region pci_regions[] = {
void pci_init_board(void)
{
int i;
int warmboot;
volatile immap_t *immr;
volatile pcictrl83xx_t *pci_ctrl;
volatile gpio83xx_t *gpio;
@ -102,7 +101,5 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
mpc83xx_pci_init(1, reg, warmboot);
mpc83xx_pci_init(1, reg);
}

2
board/mpc8308_p1m/mpc8308_p1m.c
View File

@ -74,7 +74,7 @@ void pci_init_board(void)
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(1, pcie_reg, 0);
mpc83xx_pcie_init(1, pcie_reg);
}
#if defined(CONFIG_OF_BOARD_SETUP)

2
board/sbc8349/pci.c
View File

@ -84,5 +84,5 @@ pci_init_board(void)
udelay(2000);
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
}

5
board/sheldon/simpc8313/simpc8313.c
View File

@ -67,7 +67,6 @@ void pci_init_board(void)
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
@ -81,9 +80,7 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
mpc83xx_pci_init(1, reg, warmboot);
mpc83xx_pci_init(1, reg);
}
/*

2
board/tqc/tqm834x/pci.c
View File

@ -112,5 +112,5 @@ pci_init_board(void)
udelay(2000);
mpc83xx_pci_init(1, reg, 0);
mpc83xx_pci_init(1, reg);
}

5
board/ve8313/ve8313.c
View File

@ -184,7 +184,6 @@ void pci_init_board(void)
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
setbits_be32(&clk->occr, 0xe0000000);
@ -198,9 +197,7 @@ void pci_init_board(void)
out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
mpc83xx_pci_init(1, reg, warmboot);
mpc83xx_pci_init(1, reg);
}
#endif

4
include/mpc83xx.h
View File

@ -1264,9 +1264,9 @@
#ifndef __ASSEMBLY__
struct pci_region;
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
void mpc83xx_pcislave_unlock(int bus);
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot);
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
#endif
#endif /* __MPC83XX_H__ */