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Blackfin: convert plat-nand code to GPIO framework

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Use the new GPIO framework code in both the Blackfin arch and the
nand_plat driver to simplify things greatly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2010-07-05 04:55:05 -04:00 committed by Scott Wood
parent bc1a884686
commit 67ceefa79b
4 changed files with 4 additions and 32 deletions
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9
include/configs/bf537-pnav.h
View File

@ -132,7 +132,6 @@
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_READY PF12
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
@ -141,13 +140,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY)
#define NAND_PLAT_INIT() \
do { \
bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
} while (0)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
/*

9
include/configs/bf537-stamp.h
View File

@ -157,7 +157,6 @@
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_READY PF3
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
@ -166,13 +165,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY)
#define NAND_PLAT_INIT() \
do { \
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \
} while (0)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
/*

8
include/configs/bf561-acvilon.h
View File

@ -145,7 +145,6 @@
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
#define BFIN_NAND_READY PF10
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
@ -154,12 +153,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY)
#define NAND_PLAT_INIT() \
do { \
bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \
bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \
} while (0)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
/*

10
include/configs/ip04.h
View File

@ -116,7 +116,6 @@
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_READY PF10
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
@ -125,14 +124,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
#define NAND_PLAT_INIT() \
do { \
bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
} while (0)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
/*