diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 6e4b1d0e22..e3f9db7b29 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -132,10 +132,14 @@ config TARGET_AXS101 config TARGET_AXS103 bool "Support Synopsys Designware SDP board AXS103" +config TARGET_HSDK + bool "Support Synpsys HS DevelopmentKit board" + endchoice source "board/abilis/tb100/Kconfig" source "board/synopsys/Kconfig" source "board/synopsys/axs10x/Kconfig" +source "board/synopsys/hsdk/Kconfig" endmenu diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index 218a6475dd..63a6694712 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_AXS101) += axs101.dtb dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb +dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb targets += $(dtb-y) diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts new file mode 100644 index 0000000000..a7b276c01e --- /dev/null +++ b/arch/arc/dts/hsdk.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &uart0; + }; + + cpu_card { + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000000>; + u-boot,dm-pre-reloc; + }; + }; + + uart0: serial0@f0005000 { + compatible = "snps,dw-apb-uart"; + reg = <0xf0005000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + ethernet@f0008000 { + #interrupt-cells = <1>; + compatible = "altr,socfpga-stmmac"; + reg = <0xf0008000 0x2000>; + phy-mode = "gmii"; + }; + + ehci@0xf0040000 { + compatible = "generic-ehci"; + reg = <0xf0040000 0x100>; + }; + + ohci@0xf0060000 { + compatible = "generic-ohci"; + reg = <0xf0060000 0x100>; + }; +}; diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig new file mode 100644 index 0000000000..e8c00a6e7d --- /dev/null +++ b/board/synopsys/hsdk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_HSDK + +config SYS_BOARD + default "hsdk" + +config SYS_VENDOR + default "synopsys" + +config SYS_CONFIG_NAME + default "hsdk" + +endif diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS new file mode 100644 index 0000000000..d034bc479d --- /dev/null +++ b/board/synopsys/hsdk/MAINTAINERS @@ -0,0 +1,5 @@ +AXS10X BOARD +M: Alexey Brodkin +S: Maintained +F: board/synopsys/hsdk/ +F: configs/hsdk_defconfig diff --git a/board/synopsys/hsdk/Makefile b/board/synopsys/hsdk/Makefile new file mode 100644 index 0000000000..d84dd03265 --- /dev/null +++ b/board/synopsys/hsdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2017 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += hsdk.o diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c new file mode 100644 index 0000000000..7b562556e6 --- /dev/null +++ b/board/synopsys/hsdk/hsdk.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000) +#define CREG_PAE (CREG_BASE + 0x180) +#define CREG_PAE_UPDATE (CREG_BASE + 0x194) +#define CREG_CPU_START (CREG_BASE + 0x400) + +int board_early_init_f(void) +{ + /* In current chip PAE support for DMA is broken, disabling it. */ + writel(0, (void __iomem *) CREG_PAE); + + /* Really apply settings made above */ + writel(1, (void __iomem *) CREG_PAE_UPDATE); + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + memset(host, 0, sizeof(struct dwmci_host)); + host->name = "Synopsys Mobile storage"; + host->ioaddr = (void *)ARC_DWMMC_BASE; + host->buswidth = 4; + host->dev_index = 0; + host->bus_hz = 100000000; + + add_dwmci(host, host->bus_hz / 2, 400000); + + return 0; +} + +#define RESET_VECTOR_ADDR 0x0 + +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + /* All cores have reset vector pointing to 0 */ + writel(addr, (void __iomem *)RESET_VECTOR_ADDR); + + /* Make sure other cores see written value in memory */ + flush_dcache_all(); +} + +void smp_kick_all_cpus(void) +{ +#define BITS_START_CORE1 1 +#define BITS_START_CORE2 2 +#define BITS_START_CORE3 3 + + int cmd = readl((void __iomem *)CREG_CPU_START); + + cmd |= (1 << BITS_START_CORE1) | + (1 << BITS_START_CORE2) | + (1 << BITS_START_CORE3); + writel(cmd, (void __iomem *)CREG_CPU_START); +} diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig new file mode 100644 index 0000000000..0018c0482e --- /dev/null +++ b/configs/hsdk_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARC=y +CONFIG_ISA_ARCV2=y +CONFIG_TARGET_HSDK=y +CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_CLK_FREQ=1000000000 +CONFIG_DEFAULT_DEVICE_TREE="hsdk" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="hsdk# " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_MMC=y +CONFIG_MMC_DW=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h new file mode 100644 index 0000000000..28ac090c05 --- /dev/null +++ b/include/configs/hsdk.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_HSDK_H_ +#define _CONFIG_HSDK_H_ + +#include + +/* + * CPU configuration + */ +#define ARC_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) +#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_1G + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTM_LEN SZ_32M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * This board might be of different versions so handle it + */ +#define CONFIG_BOARD_TYPES + +/* + * UART configuration + */ +#define CONFIG_DW_SERIAL +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 33330000 +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Ethernet PHY configuration + */ +#define CONFIG_MII + +/* + * USB 1.1 configuration + */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +/* + * Environment settings + */ +#define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE + +/* + * Environment configuration + */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE SZ_256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Misc utility configuration + */ +#define CONFIG_BOUNCE_BUFFER + +#endif /* _CONFIG_HSDK_H_ */