Merge branch 'master' of http://git.denx.de/u-boot-sunxi
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commit
672a45e828
@ -222,7 +222,12 @@ struct sunxi_ccm_reg {
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#define CCM_PLL11_CTRL_UPD (0x1 << 30)
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#define CCM_PLL11_CTRL_EN (0x1 << 31)
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#if defined(CONFIG_MACH_SUN50I)
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/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
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#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
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#else
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#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
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#endif
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#define AXI_GATE_OFFSET_DRAM 0
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@ -2,6 +2,7 @@ CONFIG_ARM=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN6I=y
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CONFIG_DRAM_ZQ=120
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CONFIG_INITIAL_USB_SCAN_DELAY=2000
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CONFIG_USB1_VBUS_PIN="PC27"
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CONFIG_USB2_VBUS_PIN=""
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CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
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@ -11,3 +11,5 @@ CONFIG_SPL=y
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_USB_EHCI_HCD=y
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CONFIG_AXP_ALDO3_VOLT=3300
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CONFIG_AXP_ALDO4_VOLT=3300
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@ -340,9 +340,16 @@ int musb_usb_probe(struct udevice *dev)
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int musb_usb_remove(struct udevice *dev)
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{
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struct musb_host_data *host = dev_get_priv(dev);
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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musb_stop(host->host);
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sunxi_usb_phy_exit(0);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
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#endif
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clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
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return 0;
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}
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@ -100,7 +100,7 @@
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* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
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#define CONFIG_SYS_INIT_RAM_SIZE 0xA000 /* 40 KiB */
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR 0x0
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#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
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@ -213,8 +213,7 @@
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#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
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#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
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/* FIXME: 40 KiB instead of 32 KiB ? */
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#define LOW_LEVEL_SRAM_STACK 0x00018000
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#define LOW_LEVEL_SRAM_STACK 0x0001A000
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#else
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/* end of 32 KiB in sram */
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