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powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB

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Changed the following DDR timing parameters for 800Mt/s:
tRRT    BL/2+1 to  BL/2
tWWT    BL/2+1 to  BL/2
tWRT    BL/2+1 to  BL/2
tRWT    BL/2+1 to  BL/2
REFINT  6500ns to  7800ns

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Poonam Aggrwal 2011-02-07 17:17:28 +05:30 committed by Kumar Gala
parent 3313b20b95
commit 66c74fca18
1 changed files with 2 additions and 2 deletions
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4
board/freescale/p1_p2_rdb/ddr.c
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@ -74,13 +74,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802
#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,