da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVM
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. When GP0[11] is high, SD0 will work but NOR flash will not. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
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@ -335,7 +335,7 @@ int board_early_init_f(void)
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int board_init(void)
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{
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#ifdef CONFIG_USE_NOR
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#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC)
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u32 val;
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#endif
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@ -386,6 +386,16 @@ int board_init(void)
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writel(val, GPIO_BANK0_REG_CLR_ADDR);
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#endif
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#ifdef CONFIG_DAVINCI_MMC
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/* Set the GPIO direction as output */
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clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
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/* Set the output as high */
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val = readl(GPIO_BANK0_REG_SET_ADDR);
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val |= (0x01 << 11);
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writel(val, GPIO_BANK0_REG_SET_ADDR);
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#endif
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#ifdef CONFIG_DRIVER_TI_EMAC
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davinci_emac_mii_mode_sel(HAS_RMII);
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#endif /* CONFIG_DRIVER_TI_EMAC */
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