fsl: csu: add an API to set R/W permission to PCIe
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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@ -6,6 +6,7 @@
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#ifndef __FSL_NS_ACCESS_H_
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#define __FSL_NS_ACCESS_H_
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#include <fsl_csu.h>
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enum csu_cslx_ind {
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CSU_CSLX_PCIE2_IO = 0,
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@ -8,6 +8,7 @@
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#include <asm/io.h>
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#include <fsl_csu.h>
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#include <asm/arch/ns_access.h>
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#include <asm/arch/fsl_serdes.h>
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void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
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{
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@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void)
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{
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enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
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}
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void set_pcie_ns_access(int pcie, u16 val)
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{
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switch (pcie) {
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#ifdef CONFIG_PCIE1
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case PCIE1:
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set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
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set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
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return;
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#endif
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#ifdef CONFIG_PCIE2
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case PCIE2:
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set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
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set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
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return;
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#endif
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#ifdef CONFIG_PCIE3
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case PCIE3:
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set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
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set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
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return;
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#endif
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default:
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debug("The PCIE%d doesn't exist!\n", pcie);
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return;
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}
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}
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@ -31,5 +31,6 @@ struct csu_ns_dev {
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void enable_layerscape_ns_access(void);
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void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
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void set_pcie_ns_access(int pcie, u16 val);
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#endif
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