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ARM: tegra: Add Tegra20 PCIe device tree node

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Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Thierry Reding 2014-12-09 22:25:13 -07:00 committed by Tom Warren
parent f315828b0d
commit 65d2465d5d
2 changed files with 60 additions and 1 deletions
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59
arch/arm/dts/tegra20.dtsi
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@ -332,6 +332,65 @@
reg = <0x7000f400 0x200>; reg = <0x7000f400 0x200>;
}; };
pcie-controller@80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
reg = <0x80003000 0x00000800 /* PADS registers */
0x80003800 0x00000200 /* AFI registers */
0x90000000 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
clocks = <&tegra_car TEGRA20_CLK_PEX>,
<&tegra_car TEGRA20_CLK_AFI>,
<&tegra_car TEGRA20_CLK_PCIE_XCLK>,
<&tegra_car TEGRA20_CLK_PLL_E>;
clock-names = "pex", "afi", "pcie_xclk", "pll_e";
status = "disabled";
pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <2>;
};
pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <2>;
};
};
usb@c5000000 { usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci"; compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>; reg = <0xc5000000 0x4000>;

2
include/dt-bindings/clock/tegra20-car.h
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@ -92,7 +92,7 @@
#define TEGRA20_CLK_OWR 71 #define TEGRA20_CLK_OWR 71
#define TEGRA20_CLK_AFI 72 #define TEGRA20_CLK_AFI 72
#define TEGRA20_CLK_CSITE 73 #define TEGRA20_CLK_CSITE 73
/* 74 */ #define TEGRA20_CLK_PCIE_XCLK 74
#define TEGRA20_CLK_AVPUCQ 75 #define TEGRA20_CLK_AVPUCQ 75
#define TEGRA20_CLK_LA 76 #define TEGRA20_CLK_LA 76
/* 77 */ /* 77 */