From 0a222d53d81cbd4f7a440a6f83e243a7b4e80544 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:24 +0100
Subject: [PATCH 01/10] fdt: Support for ISA busses
Support ISA busses in much the same way as Linux does. This allows for
ISA bus addresses to be translated, and only if CONFIG_OF_ISA_BUS is
selected in order to avoid including the code in builds which won't need
it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
common/fdt_support.c | 101 +++++++++++++++++++++++++++++++++++++++++--
drivers/core/Kconfig | 23 ++++++++++
2 files changed, 121 insertions(+), 3 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42e5d8a1d2..96b5d0aa4e 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -964,10 +964,21 @@ static void of_dump_addr(const char *s, const fdt32_t *addr, int na)
static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { }
#endif
-/* Callbacks for bus specific translators */
+/**
+ * struct of_bus - Callbacks for bus specific translators
+ * @match: Return non-zero if the node whose parent is at
+ * parentoffset in the FDT blob corresponds to a bus
+ * of this type, otherwise return zero. If NULL a match
+ * is assumed.
+ *
+ * Each bus type will include a struct of_bus in the of_busses array,
+ * providing implementations of some or all of the functions used to
+ * match the bus & handle address translation for its children.
+ */
struct of_bus {
const char *name;
const char *addresses;
+ int (*match)(void *blob, int parentoffset);
void (*count_cells)(void *blob, int parentoffset,
int *addrc, int *sizec);
u64 (*map)(fdt32_t *addr, const fdt32_t *range,
@@ -1022,8 +1033,70 @@ static int of_bus_default_translate(fdt32_t *addr, u64 offset, int na)
return 0;
}
+#ifdef CONFIG_OF_ISA_BUS
+
+/* ISA bus translator */
+static int of_bus_isa_match(void *blob, int parentoffset)
+{
+ const char *name;
+
+ name = fdt_get_name(blob, parentoffset, NULL);
+ if (!name)
+ return 0;
+
+ return !strcmp(name, "isa");
+}
+
+static void of_bus_isa_count_cells(void *blob, int parentoffset,
+ int *addrc, int *sizec)
+{
+ if (addrc)
+ *addrc = 2;
+ if (sizec)
+ *sizec = 1;
+}
+
+static u64 of_bus_isa_map(fdt32_t *addr, const fdt32_t *range,
+ int na, int ns, int pna)
+{
+ u64 cp, s, da;
+
+ /* Check address type match */
+ if ((addr[0] ^ range[0]) & cpu_to_be32(1))
+ return OF_BAD_ADDR;
+
+ cp = of_read_number(range + 1, na - 1);
+ s = of_read_number(range + na + pna, ns);
+ da = of_read_number(addr + 1, na - 1);
+
+ debug("OF: ISA map, cp=%" PRIu64 ", s=%" PRIu64
+ ", da=%" PRIu64 "\n", cp, s, da);
+
+ if (da < cp || da >= (cp + s))
+ return OF_BAD_ADDR;
+ return da - cp;
+}
+
+static int of_bus_isa_translate(fdt32_t *addr, u64 offset, int na)
+{
+ return of_bus_default_translate(addr + 1, offset, na - 1);
+}
+
+#endif /* CONFIG_OF_ISA_BUS */
+
/* Array of bus specific translators */
static struct of_bus of_busses[] = {
+#ifdef CONFIG_OF_ISA_BUS
+ /* ISA */
+ {
+ .name = "isa",
+ .addresses = "reg",
+ .match = of_bus_isa_match,
+ .count_cells = of_bus_isa_count_cells,
+ .map = of_bus_isa_map,
+ .translate = of_bus_isa_translate,
+ },
+#endif /* CONFIG_OF_ISA_BUS */
/* Default */
{
.name = "default",
@@ -1034,6 +1107,28 @@ static struct of_bus of_busses[] = {
},
};
+static struct of_bus *of_match_bus(void *blob, int parentoffset)
+{
+ struct of_bus *bus;
+
+ if (ARRAY_SIZE(of_busses) == 1)
+ return of_busses;
+
+ for (bus = of_busses; bus; bus++) {
+ if (!bus->match || bus->match(blob, parentoffset))
+ return bus;
+ }
+
+ /*
+ * We should always have matched the default bus at least, since
+ * it has a NULL match field. If we didn't then it somehow isn't
+ * in the of_busses array or something equally catastrophic has
+ * gone wrong.
+ */
+ assert(0);
+ return NULL;
+}
+
static int of_translate_one(void * blob, int parent, struct of_bus *bus,
struct of_bus *pbus, fdt32_t *addr,
int na, int ns, int pna, const char *rprop)
@@ -1113,7 +1208,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in
parent = fdt_parent_offset(blob, node_offset);
if (parent < 0)
goto bail;
- bus = &of_busses[0];
+ bus = of_match_bus(blob, parent);
/* Cound address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
@@ -1142,7 +1237,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in
}
/* Get new parent bus and counts */
- pbus = &of_busses[0];
+ pbus = of_match_bus(blob, parent);
pbus->count_cells(blob, parent, &pna, &pns);
if (!OF_CHECK_COUNTS(pna, pns)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index c5c9d2a42e..87495614c2 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -178,4 +178,27 @@ config SPL_OF_TRANSLATE
used for the address translation. This function is faster and
smaller in size than fdt_translate_address().
+config OF_ISA_BUS
+ bool
+ depends on OF_TRANSLATE
+ help
+ Is this option is enabled then support for the ISA bus will
+ be included for addresses read from DT. This is something that
+ should be known to be required or not based upon the board
+ being targetted, and whether or not it makes use of an ISA bus.
+
+ The bus is matched based upon its node name equalling "isa". The
+ busses #address-cells should equal 2, with the first cell being
+ used to hold flags & flag 0x1 indicating that the address range
+ should be accessed using I/O port in/out accessors. The second
+ cell holds the offset into ISA bus address space. The #size-cells
+ property should equal 1, and of course holds the size of the
+ address range used by a device.
+
+ If this option is not enabled then support for the ISA bus is
+ not included and any such busses used in DT will be treated as
+ typical simple-bus compatible busses. This will lead to
+ mistranslation of device addresses, so ensure that this is
+ enabled if your board does include an ISA bus.
+
endmenu
From 49717b18be6760cc560767ed3a0c72ecfd3cb076 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:25 +0100
Subject: [PATCH 02/10] fdt: Document the rest of struct of_bus
Provide some documentation for the fields of struct of_bus, for
consistency with that provided for the new match field.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
common/fdt_support.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 96b5d0aa4e..5d8eb12f10 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -966,10 +966,29 @@ static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { }
/**
* struct of_bus - Callbacks for bus specific translators
+ * @name: A string used to identify this bus in debug output.
+ * @addresses: The name of the DT property from which addresses are
+ * to be read, typically "reg".
* @match: Return non-zero if the node whose parent is at
* parentoffset in the FDT blob corresponds to a bus
* of this type, otherwise return zero. If NULL a match
* is assumed.
+ * @count_cells:Count how many cells (be32 values) a node whose parent
+ * is at parentoffset in the FDT blob will require to
+ * represent its address (written to *addrc) & size
+ * (written to *sizec).
+ * @map: Map the address addr from the address space of this
+ * bus to that of its parent, making use of the ranges
+ * read from DT to an array at range. na and ns are the
+ * number of cells (be32 values) used to hold and address
+ * or size, respectively, for this bus. pna is the number
+ * of cells used to hold an address for the parent bus.
+ * Returns the address in the address space of the parent
+ * bus.
+ * @translate: Update the value of the address cells at addr within an
+ * FDT by adding offset to it. na specifies the number of
+ * cells used to hold the address being translated. Returns
+ * zero on success, non-zero on error.
*
* Each bus type will include a struct of_bus in the of_busses array,
* providing implementations of some or all of the functions used to
From df8ec55d52c74a9c73df549da846f5e6c5acb5ab Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:26 +0100
Subject: [PATCH 03/10] dm: ns16550: Don't map_physmem for I/O ports
If the UART is to be accessed using I/O port accessors (inb & outb) then
using map_physmem doesn't make sense, since it operates in a different
memory space. Remove the call to map_physmem when
CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses
to not be mangled by the incorrect mapping.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
drivers/serial/ns16550.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 28da9ddfd8..d7a3cf665e 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -100,7 +100,8 @@ static void ns16550_writeb(NS16550_t port, int offset, int value)
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
+ addr = (unsigned char *)plat->base + offset;
+
/*
* As far as we know it doesn't make sense to support selection of
* these options at run-time, so use the existing CONFIG options.
@@ -114,7 +115,7 @@ static int ns16550_readb(NS16550_t port, int offset)
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
+ addr = (unsigned char *)plat->base + offset;
return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
}
@@ -400,7 +401,12 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
plat->base = addr;
+#else
+ plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
+#endif
+
plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-offset", 0);
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
From 2e7eb12e5c81dedaff12b0cea2341dc681d8c726 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:27 +0100
Subject: [PATCH 04/10] malta: Tidy up UART address selection
The address of the UART differs based upon the system controller because
it's actually within the I/O port region, which is in a different
location for each system controller. Rather than handling this as 2
UARTs with the correct one selected at runtime, use I/O port accessors
for the UART such that access to it gets translated into the I/O port
region automatically.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
board/imgtec/malta/malta.c | 13 -------------
include/configs/malta.h | 4 ++--
2 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 3a9e7807c6..495504372a 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -12,7 +12,6 @@
#include <pci_gt64120.h>
#include <pci_msc01.h>
#include <rtc.h>
-#include <serial.h>
#include <asm/addrspace.h>
#include <asm/io.h>
@@ -161,18 +160,6 @@ int misc_init_r(void)
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- switch (malta_sys_con()) {
- case SYSCON_GT64120:
- return &eserial1_device;
-
- default:
- case SYSCON_MSC01:
- return &eserial2_device;
- }
-}
-
void pci_init_board(void)
{
pci_dev_t bdf;
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 04dca71036..1c3c83c25e 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -67,10 +67,10 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_PORT_MAPPED
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (115200 * 16)
-#define CONFIG_SYS_NS16550_COM1 0xb80003f8
-#define CONFIG_SYS_NS16550_COM2 0xbb0003f8
+#define CONFIG_SYS_NS16550_COM1 0x3f8
#define CONFIG_CONS_INDEX 1
/*
From 6242aa137427f6da6ca47e7a8c9a9f78ad63e00d Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:28 +0100
Subject: [PATCH 05/10] malta: Use device model & tree for UART
Make use of device model & device tree to probe the UART driver. This is
the initial step in bringing Malta up to date with driver model, and
allows for cleaner handling of the different I/O addresses for different
system controllers by specifying the ISA bus address instead of a
translated memory address.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
arch/mips/Kconfig | 4 ++++
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mti,malta.dts | 32 ++++++++++++++++++++++++++++++++
configs/malta_defconfig | 2 ++
configs/maltael_defconfig | 2 ++
include/configs/malta.h | 6 ------
6 files changed, 41 insertions(+), 6 deletions(-)
create mode 100644 arch/mips/dts/mti,malta.dts
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dc34c18258..53363e38fe 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -23,7 +23,11 @@ config TARGET_QEMU_MIPS
config TARGET_MALTA
bool "Support malta"
+ select DM
+ select DM_SERIAL
select DYNAMIC_IO_PORT_BASE
+ select OF_CONTROL
+ select OF_ISA_BUS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index a94b745550..2f04d73b83 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -4,6 +4,7 @@
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
new file mode 100644
index 0000000000..d339229c2a
--- /dev/null
+++ b/arch/mips/dts/mti,malta.dts
@@ -0,0 +1,32 @@
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00001000; /* Exception vectors */
+/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mti,malta";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ isa@0 {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0x1000>;
+
+ uart0: serial@3f8 {
+ compatible = "ns16550a";
+
+ reg = <1 0x3f8 0x40>;
+ reg-shift = <0>;
+
+ clock-frequency = <1843200>;
+
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index a16f10be6a..3c3bb16522 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -1,5 +1,6 @@
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="malta # "
# CONFIG_CMD_LOADB is not set
@@ -9,5 +10,6 @@ CONFIG_SYS_PROMPT="malta # "
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 5289797748..b245d915ef 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -1,6 +1,7 @@
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="maltael # "
# CONFIG_CMD_LOADB is not set
@@ -10,5 +11,6 @@ CONFIG_SYS_PROMPT="maltael # "
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 1c3c83c25e..e03935b573 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -65,13 +65,7 @@
* Serial driver
*/
#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_PORT_MAPPED
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (115200 * 16)
-#define CONFIG_SYS_NS16550_COM1 0x3f8
-#define CONFIG_CONS_INDEX 1
/*
* Flash configuration
From ec35e12331512cf5ed0f22005d7b6fb4ccc35969 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 11:56:39 +0100
Subject: [PATCH 06/10] MIPS: Move CONFIG_SYS_TEXT_BASE to Kconfig
Move CONFIG_SYS_TEXT_BASE to Kconfig, and add default values in board
Kconfig files matching what was present in their config headers. This
will make it cleaner to conditionalise the value for Malta based on 32
vs 64 bit builds.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---
Kconfig | 2 +-
board/dbau1x00/Kconfig | 3 +++
board/imgtec/malta/Kconfig | 3 +++
board/microchip/pic32mzda/Kconfig | 3 +++
board/micronas/vct/Kconfig | 3 +++
board/pb1x00/Kconfig | 3 +++
board/qca/ap121/Kconfig | 3 +++
board/qca/ap143/Kconfig | 3 +++
board/qemu-mips/Kconfig | 4 ++++
board/tplink/wdr4300/Kconfig | 3 +++
include/configs/ap121.h | 2 --
include/configs/ap143.h | 2 --
include/configs/dbau1x00.h | 6 ------
include/configs/malta.h | 1 -
include/configs/pb1x00.h | 6 ------
include/configs/pic32mzdask.h | 1 -
include/configs/qemu-mips.h | 1 -
include/configs/qemu-mips64.h | 1 -
include/configs/tplink_wdr4300.h | 2 --
include/configs/vct.h | 1 -
20 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/Kconfig b/Kconfig
index f53759a48e..4b46216665 100644
--- a/Kconfig
+++ b/Kconfig
@@ -268,7 +268,7 @@ config SYS_EXTRA_OPTIONS
config SYS_TEXT_BASE
depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
- (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE
+ (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS
depends on !EFI_APP
hex "Text Base"
help
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index b813adb840..342ec59cb7 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -9,6 +9,9 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "dbau1x00"
+config SYS_TEXT_BASE
+ default 0xbfc00000
+
menu "dbau1x00 board options"
choice
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 4c06d0c0d8..2bb8e8be16 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -9,4 +9,7 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "malta"
+config SYS_TEXT_BASE
+ default 0xbe000000
+
endif
diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig
index 8acb393369..4f08e98b97 100644
--- a/board/microchip/pic32mzda/Kconfig
+++ b/board/microchip/pic32mzda/Kconfig
@@ -10,4 +10,7 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "pic32mzdask"
+config SYS_TEXT_BASE
+ default 0x9d004000
+
endif
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index c518079efa..535a77b2a3 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -9,6 +9,9 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "vct"
+config SYS_TEXT_BASE
+ default 0x87000000
+
menu "vct board options"
choice
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 251db6ab63..236a4108bf 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -9,4 +9,7 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "pb1x00"
+config SYS_TEXT_BASE
+ default 0x83800000
+
endif
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index f7e768ad58..c3ecc8f62f 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -9,4 +9,7 @@ config SYS_BOARD
config SYS_CONFIG_NAME
default "ap121"
+config SYS_TEXT_BASE
+ default 0x9f000000
+
endif
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 4cdac0d06d..5ea5d6fbb0 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -9,4 +9,7 @@ config SYS_BOARD
config SYS_CONFIG_NAME
default "ap143"
+config SYS_TEXT_BASE
+ default 0x9f000000
+
endif
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 18d78b5100..3de1f44a3d 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -7,4 +7,8 @@ config SYS_CONFIG_NAME
default "qemu-mips" if 32BIT
default "qemu-mips64" if 64BIT
+config SYS_TEXT_BASE
+ default 0xbfc00000 if 32BIT
+ default 0xffffffffbfc00000 if 64BIT
+
endif
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 902abf560d..65785bdb9c 100644
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -12,4 +12,7 @@ config SYS_BOARD
config SYS_CONFIG_NAME
default "tplink_wdr4300"
+config SYS_TEXT_BASE
+ default 0xa1000000
+
endif
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 2beffa4805..6f69f31503 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_TEXT_BASE 0x9f000000
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 7b69e10be4..f907c02af9 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_TEXT_BASE 0x9f000000
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index eb0a87cd59..68d9e36b19 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -139,12 +139,6 @@
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
-/* The following #defines are needed to get flash environment right */
-/* ROM version */
-#define CONFIG_SYS_TEXT_BASE 0xbfc00000
-/* RAM version */
-/* #define CONFIG_SYS_TEXT_BASE 0x80100000 */
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
diff --git a/include/configs/malta.h b/include/configs/malta.h
index e03935b573..a36967848c 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -37,7 +37,6 @@
/*
* Memory map
*/
-#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index caf75a6b26..869768add0 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -80,12 +80,6 @@
#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
-/* The following #defines are needed to get flash environment right */
-/* ROM version */
-/* #define CONFIG_SYS_TEXT_BASE 0xbfc00000 */
-/* SDRAM version */
-#define CONFIG_SYS_TEXT_BASE 0x83800000
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 108c6a2d62..fb2e41fd92 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -10,7 +10,6 @@
#define __PIC32MZDASK_CONFIG_H
/* System Configuration */
-#define CONFIG_SYS_TEXT_BASE 0x9d004000 /* .text */
#define CONFIG_DISPLAY_BOARDINFO
/*--------------------------------------------
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 702967c4e8..246ee0173a 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -107,7 +107,6 @@
* FLASH and environment organization
*/
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 239454984a..60a3a71fbd 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -107,7 +107,6 @@
* FLASH and environment organization
*/
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 2b9e92ed2b..09a69fec09 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_TEXT_BASE 0xa1000000
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 6489e08173..68eb089394 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -32,7 +32,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
-#define CONFIG_SYS_TEXT_BASE 0x87000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
From ecc9d26062c9dd6d0752c988a54b95453c20c749 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 25 May 2016 02:17:42 +0200
Subject: [PATCH 07/10] mips: Allow overriding start.S in SPL
Certain chips, like the JZ47xx, have extreme size constraints on the
SPL size and require custom start.S . Allow overriding the start.S
the same way ARM MXS does it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
---
arch/mips/Makefile | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 655a493382..0b5dbb68fd 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -4,6 +4,12 @@
head-y := arch/mips/cpu/start.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+endif
+endif
+
libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
From 1ad3a6fb5b9eb8444281c3975de6c6b7e1549c53 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 25 May 2016 02:17:07 +0200
Subject: [PATCH 08/10] mips: Drop JZ4740 remnants
Remove the remnants of JZ4740 support.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
---
arch/mips/include/asm/global_data.h | 8 -
arch/mips/include/asm/jz4740.h | 1150 ---------------------------
2 files changed, 1158 deletions(-)
delete mode 100644 arch/mips/include/asm/jz4740.h
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 3f230b08f6..37f8ed52e6 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -15,14 +15,6 @@ struct arch_global_data {
#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
unsigned long io_port_base;
#endif
-#ifdef CONFIG_JZSOC
- /* There are other clocks in the jz4740 */
- unsigned long per_clk; /* Peripheral bus clock */
- unsigned long dev_clk; /* Device clock */
- unsigned long sys_clk;
- unsigned long tbl;
- unsigned long lastinc;
-#endif
#ifdef CONFIG_ARCH_ATH79
unsigned long id;
unsigned long soc;
diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
deleted file mode 100644
index 7a7cfff29a..0000000000
--- a/arch/mips/include/asm/jz4740.h
+++ /dev/null
@@ -1,1150 +0,0 @@
-/*
- * head file for Ingenic Semiconductor's JZ4740 CPU.
- */
-#ifndef __JZ4740_H__
-#define __JZ4740_H__
-
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-/* Boot ROM Specification */
-/* NOR Boot config */
-#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
-#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
-#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
-/* NAND Boot config */
-#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
-#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
-
-/* 1st-level interrupts */
-#define JZ4740_IRQ_I2C 1
-#define JZ4740_IRQ_UHC 3
-#define JZ4740_IRQ_UART0 9
-#define JZ4740_IRQ_SADC 12
-#define JZ4740_IRQ_MSC 14
-#define JZ4740_IRQ_RTC 15
-#define JZ4740_IRQ_SSI 16
-#define JZ4740_IRQ_CIM 17
-#define JZ4740_IRQ_AIC 18
-#define JZ4740_IRQ_ETH 19
-#define JZ4740_IRQ_DMAC 20
-#define JZ4740_IRQ_TCU2 21
-#define JZ4740_IRQ_TCU1 22
-#define JZ4740_IRQ_TCU0 23
-#define JZ4740_IRQ_UDC 24
-#define JZ4740_IRQ_GPIO3 25
-#define JZ4740_IRQ_GPIO2 26
-#define JZ4740_IRQ_GPIO1 27
-#define JZ4740_IRQ_GPIO0 28
-#define JZ4740_IRQ_IPU 29
-#define JZ4740_IRQ_LCD 30
-/* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
-#define JZ4740_IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
-
-/* Register Definitions */
-#define JZ4740_CPM_BASE 0x10000000
-#define JZ4740_INTC_BASE 0x10001000
-#define JZ4740_TCU_BASE 0x10002000
-#define JZ4740_WDT_BASE 0x10002000
-#define JZ4740_RTC_BASE 0x10003000
-#define JZ4740_GPIO_BASE 0x10010000
-#define JZ4740_AIC_BASE 0x10020000
-#define JZ4740_ICDC_BASE 0x10020000
-#define JZ4740_MSC_BASE 0x10021000
-#define JZ4740_UART0_BASE 0x10030000
-#define JZ4740_I2C_BASE 0x10042000
-#define JZ4740_SSI_BASE 0x10043000
-#define JZ4740_SADC_BASE 0x10070000
-#define JZ4740_EMC_BASE 0x13010000
-#define JZ4740_DMAC_BASE 0x13020000
-#define JZ4740_UHC_BASE 0x13030000
-#define JZ4740_UDC_BASE 0x13040000
-#define JZ4740_LCD_BASE 0x13050000
-#define JZ4740_SLCD_BASE 0x13050000
-#define JZ4740_CIM_BASE 0x13060000
-#define JZ4740_ETH_BASE 0x13100000
-
-/* 8bit Mode Register of SDRAM bank 0 */
-#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000)
-
-/* GPIO (General-Purpose I/O Ports) */
-/* = 0,1,2,3 */
-#define GPIO_PXPIN(n) \
- (JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
-#define GPIO_PXDAT(n) \
- (JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
-#define GPIO_PXDATS(n) \
- (JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
-#define GPIO_PXDATC(n) \
- (JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
-#define GPIO_PXIM(n) \
- (JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
-#define GPIO_PXIMS(n) \
- (JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
-#define GPIO_PXIMC(n) \
- (JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
-#define GPIO_PXPE(n) \
- (JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
-#define GPIO_PXPES(n) \
- (JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
-#define GPIO_PXPEC(n) \
- (JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
-#define GPIO_PXFUN(n) \
- (JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
-#define GPIO_PXFUNS(n) \
- (JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
-#define GPIO_PXFUNC(n) \
- (JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
-#define GPIO_PXSEL(n) \
- (JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
-#define GPIO_PXSELS(n) \
- (JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
-#define GPIO_PXSELC(n) \
- (JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
-#define GPIO_PXDIR(n) \
- (JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
-#define GPIO_PXDIRS(n) \
- (JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
-#define GPIO_PXDIRC(n) \
- (JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
-#define GPIO_PXTRG(n) \
- (JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
-#define GPIO_PXTRGS(n) \
- (JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
-#define GPIO_PXTRGC(n) \
- (JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
-
-/* Static Memory Control Register */
-#define EMC_SMCR_STRV_BIT 24
-#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
-#define EMC_SMCR_TAW_BIT 20
-#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
-#define EMC_SMCR_TBP_BIT 16
-#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
-#define EMC_SMCR_TAH_BIT 12
-#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
-#define EMC_SMCR_TAS_BIT 8
-#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
-#define EMC_SMCR_BW_BIT 6
-#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
-#define EMC_SMCR_BCM (1 << 3)
-#define EMC_SMCR_BL_BIT 1
-#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
-#define EMC_SMCR_SMT (1 << 0)
-
-/* Static Memory Bank Addr Config Reg */
-#define EMC_SACR_BASE_BIT 8
-#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
-#define EMC_SACR_MASK_BIT 0
-#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
-
-/* NAND Flash Control/Status Register */
-#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
-#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
-#define EMC_NFCSR_NFCE3 (1 << 5)
-#define EMC_NFCSR_NFE3 (1 << 4)
-#define EMC_NFCSR_NFCE2 (1 << 3)
-#define EMC_NFCSR_NFE2 (1 << 2)
-#define EMC_NFCSR_NFCE1 (1 << 1)
-#define EMC_NFCSR_NFE1 (1 << 0)
-
-/* NAND Flash ECC Control Register */
-#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
-#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
-#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
-#define EMC_NFECR_HAMMING (0 << 2) /* Use HAMMING Correction Algorithm */
-#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
-#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
-#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
-
-/* NAND Flash ECC Data Register */
-#define EMC_NFECC_ECC2_BIT 16
-#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
-#define EMC_NFECC_ECC1_BIT 8
-#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
-#define EMC_NFECC_ECC0_BIT 0
-#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
-
-/* NAND Flash Interrupt Status Register */
-#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
-#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
-#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
-#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
-#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
-#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
-#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
-
-/* NAND Flash Interrupt Enable Register */
-#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt */
-#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt */
-#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt */
-#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr */
-#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
-
-/* NAND Flash RS Error Report Register */
-#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
-#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
-#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
-#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
-
-/* DRAM Control Register */
-#define EMC_DMCR_BW_BIT 31
-#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
-#define EMC_DMCR_CA_BIT 26
-#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
-#define EMC_DMCR_RMODE (1 << 25)
-#define EMC_DMCR_RFSH (1 << 24)
-#define EMC_DMCR_MRSET (1 << 23)
-#define EMC_DMCR_RA_BIT 20
-#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
-#define EMC_DMCR_BA_BIT 19
-#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
-#define EMC_DMCR_PDM (1 << 18)
-#define EMC_DMCR_EPIN (1 << 17)
-#define EMC_DMCR_TRAS_BIT 13
-#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
-#define EMC_DMCR_RCD_BIT 11
-#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
-#define EMC_DMCR_TPC_BIT 8
-#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
-#define EMC_DMCR_TRWL_BIT 5
-#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
-#define EMC_DMCR_TRC_BIT 2
-#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
-#define EMC_DMCR_TCL_BIT 0
-#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
-
-/* Refresh Time Control/Status Register */
-#define EMC_RTCSR_CMF (1 << 7)
-#define EMC_RTCSR_CKS_BIT 0
-#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
-
-/* SDRAM Bank Address Configuration Register */
-#define EMC_DMAR_BASE_BIT 8
-#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
-#define EMC_DMAR_MASK_BIT 0
-#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
-
-/* Mode Register of SDRAM bank 0 */
-#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
-#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
-#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
- #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
-#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
-#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
-#define EMC_SDMR_BT_BIT 3 /* Burst Type */
-#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
- #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
- #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
-#define EMC_SDMR_BL_BIT 0 /* Burst Length */
-#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
-
-#define EMC_SDMR_CAS2_16BIT \
- (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS2_32BIT \
- (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-#define EMC_SDMR_CAS3_16BIT \
- (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS3_32BIT \
- (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-
-/* RTC Control Register */
-#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
-#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
-#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
-#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
-#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
-#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
-#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
-
-/* RTC Regulator Register */
-#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
-#define RTC_RGR_ADJC_BIT 16
-#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
-#define RTC_RGR_NC1HZ_BIT 0
-#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
-
-/* Hibernate Control Register */
-#define RTC_HCR_PD (1 << 0) /* Power Down */
-
-/* Hibernate Wakeup Filter Counter Register */
-#define RTC_HWFCR_BIT 5
-#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
-
-/* Hibernate Reset Counter Register */
-#define RTC_HRCR_BIT 5
-#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
-
-/* Hibernate Wakeup Control Register */
-#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
-
-/* Hibernate Wakeup Status Register */
-#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
-#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
-#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
-#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
-
-/* Clock Control Register */
-#define CPM_CPCCR_I2CS (1 << 31)
-#define CPM_CPCCR_CLKOEN (1 << 30)
-#define CPM_CPCCR_UCS (1 << 29)
-#define CPM_CPCCR_UDIV_BIT 23
-#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
-#define CPM_CPCCR_CE (1 << 22)
-#define CPM_CPCCR_PCS (1 << 21)
-#define CPM_CPCCR_LDIV_BIT 16
-#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
-#define CPM_CPCCR_MDIV_BIT 12
-#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
-#define CPM_CPCCR_PDIV_BIT 8
-#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
-#define CPM_CPCCR_HDIV_BIT 4
-#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
-#define CPM_CPCCR_CDIV_BIT 0
-#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
-
-/* I2S Clock Divider Register */
-#define CPM_I2SCDR_I2SDIV_BIT 0
-#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
-
-/* LCD Pixel Clock Divider Register */
-#define CPM_LPCDR_PIXDIV_BIT 0
-#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
-
-/* MSC Clock Divider Register */
-#define CPM_MSCCDR_MSCDIV_BIT 0
-#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
-
-/* PLL Control Register */
-#define CPM_CPPCR_PLLM_BIT 23
-#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
-#define CPM_CPPCR_PLLN_BIT 18
-#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
-#define CPM_CPPCR_PLLOD_BIT 16
-#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
-#define CPM_CPPCR_PLLS (1 << 10)
-#define CPM_CPPCR_PLLBP (1 << 9)
-#define CPM_CPPCR_PLLEN (1 << 8)
-#define CPM_CPPCR_PLLST_BIT 0
-#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
-
-/* Low Power Control Register */
-#define CPM_LCR_DOZE_DUTY_BIT 3
-#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
-#define CPM_LCR_DOZE_ON (1 << 2)
-#define CPM_LCR_LPM_BIT 0
-#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
- #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
- #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
-
-/* Clock Gate Register */
-#define CPM_CLKGR_UART1 (1 << 15)
-#define CPM_CLKGR_UHC (1 << 14)
-#define CPM_CLKGR_IPU (1 << 13)
-#define CPM_CLKGR_DMAC (1 << 12)
-#define CPM_CLKGR_UDC (1 << 11)
-#define CPM_CLKGR_LCD (1 << 10)
-#define CPM_CLKGR_CIM (1 << 9)
-#define CPM_CLKGR_SADC (1 << 8)
-#define CPM_CLKGR_MSC (1 << 7)
-#define CPM_CLKGR_AIC1 (1 << 6)
-#define CPM_CLKGR_AIC2 (1 << 5)
-#define CPM_CLKGR_SSI (1 << 4)
-#define CPM_CLKGR_I2C (1 << 3)
-#define CPM_CLKGR_RTC (1 << 2)
-#define CPM_CLKGR_TCU (1 << 1)
-#define CPM_CLKGR_UART0 (1 << 0)
-
-/* Sleep Control Register */
-#define CPM_SCR_O1ST_BIT 8
-#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
-#define CPM_SCR_UDCPHY_ENABLE (1 << 6)
-#define CPM_SCR_USBPHY_DISABLE (1 << 7)
-#define CPM_SCR_OSC_ENABLE (1 << 4)
-
-/* Hibernate Control Register */
-#define CPM_HCR_PD (1 << 0)
-
-/* Wakeup Filter Counter Register in Hibernate Mode */
-#define CPM_HWFCR_TIME_BIT 0
-#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
-
-/* Reset Counter Register in Hibernate Mode */
-#define CPM_HRCR_TIME_BIT 0
-#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
-
-/* Wakeup Control Register in Hibernate Mode */
-#define CPM_HWCR_WLE_LOW (0 << 2)
-#define CPM_HWCR_WLE_HIGH (1 << 2)
-#define CPM_HWCR_PIN_WAKEUP (1 << 1)
-#define CPM_HWCR_RTC_WAKEUP (1 << 0)
-
-/* Wakeup Status Register in Hibernate Mode */
-#define CPM_HWSR_WSR_PIN (1 << 1)
-#define CPM_HWSR_WSR_RTC (1 << 0)
-
-/* Reset Status Register */
-#define CPM_RSR_HR (1 << 2)
-#define CPM_RSR_WR (1 << 1)
-#define CPM_RSR_PR (1 << 0)
-
-/* Register definitions */
-#define TCU_TCSR_PWM_SD (1 << 9)
-#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
-#define TCU_TCSR_PWM_EN (1 << 7)
-#define TCU_TCSR_PRESCALE_BIT 3
-#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_EXT_EN (1 << 2)
-#define TCU_TCSR_RTC_EN (1 << 1)
-#define TCU_TCSR_PCK_EN (1 << 0)
-
-#define TCU_TER_TCEN5 (1 << 5)
-#define TCU_TER_TCEN4 (1 << 4)
-#define TCU_TER_TCEN3 (1 << 3)
-#define TCU_TER_TCEN2 (1 << 2)
-#define TCU_TER_TCEN1 (1 << 1)
-#define TCU_TER_TCEN0 (1 << 0)
-
-#define TCU_TESR_TCST5 (1 << 5)
-#define TCU_TESR_TCST4 (1 << 4)
-#define TCU_TESR_TCST3 (1 << 3)
-#define TCU_TESR_TCST2 (1 << 2)
-#define TCU_TESR_TCST1 (1 << 1)
-#define TCU_TESR_TCST0 (1 << 0)
-
-#define TCU_TECR_TCCL5 (1 << 5)
-#define TCU_TECR_TCCL4 (1 << 4)
-#define TCU_TECR_TCCL3 (1 << 3)
-#define TCU_TECR_TCCL2 (1 << 2)
-#define TCU_TECR_TCCL1 (1 << 1)
-#define TCU_TECR_TCCL0 (1 << 0)
-
-#define TCU_TFR_HFLAG5 (1 << 21)
-#define TCU_TFR_HFLAG4 (1 << 20)
-#define TCU_TFR_HFLAG3 (1 << 19)
-#define TCU_TFR_HFLAG2 (1 << 18)
-#define TCU_TFR_HFLAG1 (1 << 17)
-#define TCU_TFR_HFLAG0 (1 << 16)
-#define TCU_TFR_FFLAG5 (1 << 5)
-#define TCU_TFR_FFLAG4 (1 << 4)
-#define TCU_TFR_FFLAG3 (1 << 3)
-#define TCU_TFR_FFLAG2 (1 << 2)
-#define TCU_TFR_FFLAG1 (1 << 1)
-#define TCU_TFR_FFLAG0 (1 << 0)
-
-#define TCU_TFSR_HFLAG5 (1 << 21)
-#define TCU_TFSR_HFLAG4 (1 << 20)
-#define TCU_TFSR_HFLAG3 (1 << 19)
-#define TCU_TFSR_HFLAG2 (1 << 18)
-#define TCU_TFSR_HFLAG1 (1 << 17)
-#define TCU_TFSR_HFLAG0 (1 << 16)
-#define TCU_TFSR_FFLAG5 (1 << 5)
-#define TCU_TFSR_FFLAG4 (1 << 4)
-#define TCU_TFSR_FFLAG3 (1 << 3)
-#define TCU_TFSR_FFLAG2 (1 << 2)
-#define TCU_TFSR_FFLAG1 (1 << 1)
-#define TCU_TFSR_FFLAG0 (1 << 0)
-
-#define TCU_TFCR_HFLAG5 (1 << 21)
-#define TCU_TFCR_HFLAG4 (1 << 20)
-#define TCU_TFCR_HFLAG3 (1 << 19)
-#define TCU_TFCR_HFLAG2 (1 << 18)
-#define TCU_TFCR_HFLAG1 (1 << 17)
-#define TCU_TFCR_HFLAG0 (1 << 16)
-#define TCU_TFCR_FFLAG5 (1 << 5)
-#define TCU_TFCR_FFLAG4 (1 << 4)
-#define TCU_TFCR_FFLAG3 (1 << 3)
-#define TCU_TFCR_FFLAG2 (1 << 2)
-#define TCU_TFCR_FFLAG1 (1 << 1)
-#define TCU_TFCR_FFLAG0 (1 << 0)
-
-#define TCU_TMR_HMASK5 (1 << 21)
-#define TCU_TMR_HMASK4 (1 << 20)
-#define TCU_TMR_HMASK3 (1 << 19)
-#define TCU_TMR_HMASK2 (1 << 18)
-#define TCU_TMR_HMASK1 (1 << 17)
-#define TCU_TMR_HMASK0 (1 << 16)
-#define TCU_TMR_FMASK5 (1 << 5)
-#define TCU_TMR_FMASK4 (1 << 4)
-#define TCU_TMR_FMASK3 (1 << 3)
-#define TCU_TMR_FMASK2 (1 << 2)
-#define TCU_TMR_FMASK1 (1 << 1)
-#define TCU_TMR_FMASK0 (1 << 0)
-
-#define TCU_TMSR_HMST5 (1 << 21)
-#define TCU_TMSR_HMST4 (1 << 20)
-#define TCU_TMSR_HMST3 (1 << 19)
-#define TCU_TMSR_HMST2 (1 << 18)
-#define TCU_TMSR_HMST1 (1 << 17)
-#define TCU_TMSR_HMST0 (1 << 16)
-#define TCU_TMSR_FMST5 (1 << 5)
-#define TCU_TMSR_FMST4 (1 << 4)
-#define TCU_TMSR_FMST3 (1 << 3)
-#define TCU_TMSR_FMST2 (1 << 2)
-#define TCU_TMSR_FMST1 (1 << 1)
-#define TCU_TMSR_FMST0 (1 << 0)
-
-#define TCU_TMCR_HMCL5 (1 << 21)
-#define TCU_TMCR_HMCL4 (1 << 20)
-#define TCU_TMCR_HMCL3 (1 << 19)
-#define TCU_TMCR_HMCL2 (1 << 18)
-#define TCU_TMCR_HMCL1 (1 << 17)
-#define TCU_TMCR_HMCL0 (1 << 16)
-#define TCU_TMCR_FMCL5 (1 << 5)
-#define TCU_TMCR_FMCL4 (1 << 4)
-#define TCU_TMCR_FMCL3 (1 << 3)
-#define TCU_TMCR_FMCL2 (1 << 2)
-#define TCU_TMCR_FMCL1 (1 << 1)
-#define TCU_TMCR_FMCL0 (1 << 0)
-
-#define TCU_TSR_WDTS (1 << 16)
-#define TCU_TSR_STOP5 (1 << 5)
-#define TCU_TSR_STOP4 (1 << 4)
-#define TCU_TSR_STOP3 (1 << 3)
-#define TCU_TSR_STOP2 (1 << 2)
-#define TCU_TSR_STOP1 (1 << 1)
-#define TCU_TSR_STOP0 (1 << 0)
-
-#define TCU_TSSR_WDTSS (1 << 16)
-#define TCU_TSSR_STPS5 (1 << 5)
-#define TCU_TSSR_STPS4 (1 << 4)
-#define TCU_TSSR_STPS3 (1 << 3)
-#define TCU_TSSR_STPS2 (1 << 2)
-#define TCU_TSSR_STPS1 (1 << 1)
-#define TCU_TSSR_STPS0 (1 << 0)
-
-#define TCU_TSSR_WDTSC (1 << 16)
-#define TCU_TSSR_STPC5 (1 << 5)
-#define TCU_TSSR_STPC4 (1 << 4)
-#define TCU_TSSR_STPC3 (1 << 3)
-#define TCU_TSSR_STPC2 (1 << 2)
-#define TCU_TSSR_STPC1 (1 << 1)
-#define TCU_TSSR_STPC0 (1 << 0)
-
-/* Register definition */
-#define WDT_TCSR_PRESCALE_BIT 3
-#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
-#define WDT_TCSR_EXT_EN (1 << 2)
-#define WDT_TCSR_RTC_EN (1 << 1)
-#define WDT_TCSR_PCK_EN (1 << 0)
-#define WDT_TCER_TCEN (1 << 0)
-
-/*
- * Define macros for UART_IER
- * UART Interrupt Enable Register
- */
-#define UART_IER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
-#define UART_IER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
-#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
-#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
-#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
-
-/*
- * Define macros for UART_ISR
- * UART Interrupt Status Register
- */
-#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
-#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
-#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
-#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
-#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
-#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
-/* FIFO mode select, set when UART_FCR.FE is set to 1 */
-#define UART_ISR_FFMS (3 << 6)
-#define UART_ISR_FFMS_NO_FIFO (0 << 6)
-#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
-
-/*
- * Define macros for UART_FCR
- * UART FIFO Control Register
- */
-#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
-#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
-#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
-#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
-#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
-#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
-#define UART_FCR_RTRG_1 (0 << 6)
-#define UART_FCR_RTRG_4 (1 << 6)
-#define UART_FCR_RTRG_8 (2 << 6)
-#define UART_FCR_RTRG_15 (3 << 6)
-
-/*
- * Define macros for UART_LCR
- * UART Line Control Register
- */
-#define UART_LCR_WLEN (3 << 0) /* word length */
-#define UART_LCR_WLEN_5 (0 << 0)
-#define UART_LCR_WLEN_6 (1 << 0)
-#define UART_LCR_WLEN_7 (2 << 0)
-#define UART_LCR_WLEN_8 (3 << 0)
-#define UART_LCR_STOP (1 << 2)
- /* 0: 1 stop bit when word length is 5,6,7,8
- 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_1 (0 << 2)
- /* 0: 1 stop bit when word length is 5,6,7,8
- 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_2 (1 << 2)
- /* 0: 1 stop bit when word length is 5,6,7,8
- 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-
-#define UART_LCR_PE (1 << 3) /* 0: parity disable */
-#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
-#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
-#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
-/* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
-#define UART_LCR_DLAB (1 << 7)
-
-/*
- * Define macros for UART_LSR
- * UART Line Status Register
- */
-/* 0: receive FIFO is empty 1: receive data is ready */
-#define UART_LSR_DR (1 << 0)
-/* 0: no overrun error */
-#define UART_LSR_ORER (1 << 1)
-/* 0: no parity error */
-#define UART_LSR_PER (1 << 2)
-/* 0; no framing error */
-#define UART_LSR_FER (1 << 3)
-/* 0: no break detected 1: receive a break signal */
-#define UART_LSR_BRK (1 << 4)
-/* 1: transmit FIFO half "empty" */
-#define UART_LSR_TDRQ (1 << 5)
-/* 1: transmit FIFO and shift registers empty */
-#define UART_LSR_TEMT (1 << 6)
-/* 0: no receive error 1: receive error in FIFO mode */
-#define UART_LSR_RFER (1 << 7)
-
-/*
- * Define macros for UART_MCR
- * UART Modem Control Register
- */
-#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
-#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
-/* 0: UART_MSR.RI is set to 0 and RI_ input high */
-#define UART_MCR_OUT1 (1 << 2)
-/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
-#define UART_MCR_OUT2 (1 << 3)
-#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
-#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
-
-/*
- * Define macros for UART_MSR
- * UART Modem Status Register
- */
-#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ since last read */
-#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ since last read */
-#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ since last read */
-#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ since last read */
-#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
-#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
-#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
-#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
-
-/*
- * Define macros for SIRCR
- * Slow IrDA Control Register
- */
-#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */
-#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */
-#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
- 1: 0 pulse width is 1.6us for 115.2Kbps */
-#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
-#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
-
-/* MSC Clock and Control Register (MSC_STRPCL) */
-#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
-#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
-#define MSC_STRPCL_START_READWAIT (1 << 5)
-#define MSC_STRPCL_STOP_READWAIT (1 << 4)
-#define MSC_STRPCL_RESET (1 << 3)
-#define MSC_STRPCL_START_OP (1 << 2)
-#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
-#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-
-/* MSC Status Register (MSC_STAT) */
-#define MSC_STAT_IS_RESETTING (1 << 15)
-#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
-#define MSC_STAT_PRG_DONE (1 << 13)
-#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
-#define MSC_STAT_END_CMD_RES (1 << 11)
-#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
-#define MSC_STAT_IS_READWAIT (1 << 9)
-#define MSC_STAT_CLK_EN (1 << 8)
-#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
-#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
-#define MSC_STAT_CRC_RES_ERR (1 << 5)
-#define MSC_STAT_CRC_READ_ERROR (1 << 4)
-#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
-#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No error on transmission of data */
- #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* Card observed erroneous transmission of data */
- #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No CRC status is sent back */
- #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-#define MSC_STAT_TIME_OUT_RES (1 << 1)
-#define MSC_STAT_TIME_OUT_READ (1 << 0)
-
-/* MSC Bus Clock Control Register (MSC_CLKRT) */
-#define MSC_CLKRT_CLK_RATE_BIT 0
-#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT)
-
-/* MSC Command Sequence Control Register (MSC_CMDAT) */
-#define MSC_CMDAT_IO_ABORT (1 << 11)
-#define MSC_CMDAT_BUS_WIDTH_BIT 9
-#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_DMA_EN (1 << 8)
-#define MSC_CMDAT_INIT (1 << 7)
-#define MSC_CMDAT_BUSY (1 << 6)
-#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
-#define MSC_CMDAT_WRITE (1 << 4)
-#define MSC_CMDAT_READ (0 << 4)
-#define MSC_CMDAT_DATA_EN (1 << 3)
-#define MSC_CMDAT_RESPONSE_BIT 0
-#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT)
-
-/* MSC Interrupts Mask Register (MSC_IMASK) */
-#define MSC_IMASK_SDIO (1 << 7)
-#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
-#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
-#define MSC_IMASK_END_CMD_RES (1 << 2)
-#define MSC_IMASK_PRG_DONE (1 << 1)
-#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
-
-#ifndef __ASSEMBLY__
-/* INTC (Interrupt Controller) */
-struct jz4740_intc {
- uint32_t isr; /* interrupt source register */
- uint32_t imr; /* interrupt mask register */
- uint32_t imsr; /* interrupt mask set register */
- uint32_t imcr; /* interrupt mask clear register */
- uint32_t ipr; /* interrupt pending register */
-};
-
-/* RTC */
-struct jz4740_rtc {
- uint32_t rcr; /* rtc control register */
- uint32_t rsr; /* rtc second register */
- uint32_t rsar; /* rtc second alarm register */
- uint32_t rgr; /* rtc regulator register */
- uint32_t hcr; /* hibernate control register */
- uint32_t hwfcr; /* hibernate wakeup filter counter reg */
- uint32_t hrcr; /* hibernate reset counter reg */
- uint32_t hwcr; /* hibernate wakeup control register */
- uint32_t hwrsr; /* hibernate wakeup status reg */
- uint32_t hspr; /* scratch pattern register */
-};
-
-/* CPM (Clock reset and Power control Management) */
-struct jz4740_cpm {
- uint32_t cpccr; /* 0x00 clock control reg */
- uint32_t lcr; /* 0x04 low power control reg */
- uint32_t rsr; /* 0x08 reset status reg */
- uint32_t pad00;
- uint32_t cppcr; /* 0x10 pll control reg */
- uint32_t pad01[3];
- uint32_t clkgr; /* 0x20 clock gate reg */
- uint32_t scr; /* 0x24 sleep control reg */
- uint32_t pad02[14];
- uint32_t i2scd; /* 0x60 I2S device clock divider reg */
- uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */
- uint32_t msccdr; /* 0x68 MSC device clock divider reg */
- uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */
- uint32_t uhcts; /* 0x70 UHC PHY test point reg */
- uint32_t ssicd; /* 0x74 SSI clock divider reg */
-};
-
-/* TCU (Timer Counter Unit) */
-struct jz4740_tcu {
- uint32_t pad00[4];
- uint32_t ter; /* 0x10 Timer Counter Enable Register */
- uint32_t tesr; /* 0x14 Timer Counter Enable Set Register */
- uint32_t tecr; /* 0x18 Timer Counter Enable Clear Register */
- uint32_t tsr; /* 0x1C Timer Stop Register */
- uint32_t tfr; /* 0x20 Timer Flag Register */
- uint32_t tfsr; /* 0x24 Timer Flag Set Register */
- uint32_t tfcr; /* 0x28 Timer Flag Clear Register */
- uint32_t tssr; /* 0x2C Timer Stop Set Register */
- uint32_t tmr; /* 0x30 Timer Mask Register */
- uint32_t tmsr; /* 0x34 Timer Mask Set Register */
- uint32_t tmcr; /* 0x38 Timer Mask Clear Register */
- uint32_t tscr; /* 0x3C Timer Stop Clear Register */
- uint32_t tdfr0; /* 0x40 Timer Data Full Register */
- uint32_t tdhr0; /* 0x44 Timer Data Half Register */
- uint32_t tcnt0; /* 0x48 Timer Counter Register */
- uint32_t tcsr0; /* 0x4C Timer Control Register */
- uint32_t tdfr1; /* 0x50 */
- uint32_t tdhr1; /* 0x54 */
- uint32_t tcnt1; /* 0x58 */
- uint32_t tcsr1; /* 0x5C */
- uint32_t tdfr2; /* 0x60 */
- uint32_t tdhr2; /* 0x64 */
- uint32_t tcnt2; /* 0x68 */
- uint32_t tcsr2; /* 0x6C */
- uint32_t tdfr3; /* 0x70 */
- uint32_t tdhr3; /* 0x74 */
- uint32_t tcnt3; /* 0x78 */
- uint32_t tcsr3; /* 0x7C */
- uint32_t tdfr4; /* 0x80 */
- uint32_t tdhr4; /* 0x84 */
- uint32_t tcnt4; /* 0x88 */
- uint32_t tcsr4; /* 0x8C */
- uint32_t tdfr5; /* 0x90 */
- uint32_t tdhr5; /* 0x94 */
- uint32_t tcnt5; /* 0x98 */
- uint32_t tcsr5; /* 0x9C */
-};
-
-/* WDT (WatchDog Timer) */
-struct jz4740_wdt {
- uint16_t tdr; /* 0x00 watchdog timer data reg*/
- uint16_t pad00;
- uint8_t tcer; /* 0x04 watchdog counter enable reg*/
- uint8_t pad01[3];
- uint16_t tcnt; /* 0x08 watchdog timer counter*/
- uint16_t pad02;
- uint16_t tcsr; /* 0x0C watchdog timer control reg*/
- uint16_t pad03;
-};
-
-struct jz4740_uart {
- uint8_t rbr_thr_dllr;
- /* 0x00 R 8b receive buffer reg */
- /* 0x00 W 8b transmit hold reg */
- /* 0x00 RW 8b divisor latch low reg */
- uint8_t pad00[3];
- uint8_t dlhr_ier;
- /* 0x04 RW 8b divisor latch high reg */
- /* 0x04 RW 8b interrupt enable reg */
- uint8_t pad01[3];
- uint8_t iir_fcr;
- /* 0x08 R 8b interrupt identification reg */
- /* 0x08 W 8b FIFO control reg */
- uint8_t pad02[3];
- uint8_t lcr; /* 0x0C RW 8b Line control reg */
- uint8_t pad03[3];
- uint8_t mcr; /* 0x10 RW 8b modem control reg */
- uint8_t pad04[3];
- uint8_t lsr; /* 0x14 R 8b line status reg */
- uint8_t pad05[3];
- uint8_t msr; /* 0x18 R 8b modem status reg */
- uint8_t pad06[3];
- uint8_t spr; /* 0x1C RW 8b scratch pad reg */
- uint8_t pad07[3];
- uint8_t isr; /* 0x20 RW 8b infrared selection reg */
- uint8_t pad08[3];
- uint8_t umr; /* 0x24 RW 8b */
-};
-
-/* MSC */
-struct jz4740_msc {
- uint16_t strpcl;/* 0x00 */
- uint32_t stat; /* 0x04 */
- uint16_t clkrt; /* 0x08 */
- uint32_t cmdat; /* 0x0C */
- uint16_t resto; /* 0x10 */
- uint16_t rdto; /* 0x14 */
- uint16_t blklen;/* 0x18 */
- uint16_t nob; /* 0x1C */
- uint16_t snob; /* 0x20 */
- uint16_t imask; /* 0x24 */
- uint16_t ireg; /* 0x28 */
- uint8_t cmd; /* 0x2C */
- uint32_t arg; /* 0x30 */
- uint16_t res; /* 0x34 */
- uint32_t rxfifo;/* 0x38 */
- uint32_t txfifo;/* 0x3C */
-};
-
-/* External Memory Controller */
-struct jz4740_emc {
- uint32_t bcr; /* 0x00 BCR */
- uint32_t pad00[3];
- uint32_t smcr[5];
- /* x10 Static Memory Control Register 0 */
- /* x14 Static Memory Control Register 1 */
- /* x18 Static Memory Control Register 2 */
- /* x1c Static Memory Control Register 3 */
- /* x20 Static Memory Control Register 4 */
- uint32_t pad01[3];
- uint32_t sacr[5];
- /* x30 Static Memory Bank 0 Addr Config Reg */
- /* x34 Static Memory Bank 1 Addr Config Reg */
- /* x38 Static Memory Bank 2 Addr Config Reg */
- /* x3c Static Memory Bank 3 Addr Config Reg */
- /* x40 Static Memory Bank 4 Addr Config Reg */
- uint32_t pad02[3];
- uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */
-
- uint32_t pad03[11];
- uint32_t dmcr; /* x80 DRAM Control Register */
- uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */
- uint16_t pad04;
- uint16_t rtcnt; /* x88 Refresh Timer Counter */
- uint16_t pad05;
- uint16_t rtcor; /* x8c Refresh Time Constant Register */
- uint16_t pad06;
- uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */
- uint32_t pad07[27];
- uint32_t nfecr; /* x100 NAND Flash ECC Control Register */
- uint32_t nfecc; /* x104 NAND Flash ECC Data Register */
- uint8_t nfpar[12];
- /* x108 NAND Flash RS Parity 0 Register */
- /* x10c NAND Flash RS Parity 1 Register */
- /* x110 NAND Flash RS Parity 2 Register */
- uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */
- uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */
- uint32_t nferr[4];
- /* x11c NAND Flash RS Error Report 0 Register */
- /* x120 NAND Flash RS Error Report 1 Register */
- /* x124 NAND Flash RS Error Report 2 Register */
- /* x128 NAND Flash RS Error Report 3 Register */
-};
-
-#define __gpio_as_nand() \
-do { \
- writel(0x02018000, GPIO_PXFUNS(1)); \
- writel(0x02018000, GPIO_PXSELC(1)); \
- writel(0x02018000, GPIO_PXPES(1)); \
- writel(0x30000000, GPIO_PXFUNS(2)); \
- writel(0x30000000, GPIO_PXSELC(2)); \
- writel(0x30000000, GPIO_PXPES(2)); \
- writel(0x40000000, GPIO_PXFUNC(2)); \
- writel(0x40000000, GPIO_PXSELC(2)); \
- writel(0x40000000, GPIO_PXDIRC(2)); \
- writel(0x40000000, GPIO_PXPES(2)); \
- writel(0x00400000, GPIO_PXFUNS(1)); \
- writel(0x00400000, GPIO_PXSELC(1)); \
-} while (0)
-
-#define __gpio_as_sdram_16bit_4720() \
-do { \
- writel(0x5442bfaa, GPIO_PXFUNS(0)); \
- writel(0x5442bfaa, GPIO_PXSELC(0)); \
- writel(0x5442bfaa, GPIO_PXPES(0)); \
- writel(0x81f9ffff, GPIO_PXFUNS(1)); \
- writel(0x81f9ffff, GPIO_PXSELC(1)); \
- writel(0x81f9ffff, GPIO_PXPES(1)); \
- writel(0x01000000, GPIO_PXFUNS(2)); \
- writel(0x01000000, GPIO_PXSELC(2)); \
- writel(0x01000000, GPIO_PXPES(2)); \
-} while (0)
-
-#define __gpio_as_lcd_18bit() \
-do { \
- writel(0x003fffff, GPIO_PXFUNS(2)); \
- writel(0x003fffff, GPIO_PXSELC(2)); \
- writel(0x003fffff, GPIO_PXPES(2)); \
-} while (0)
-
-/* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */
-#define __gpio_as_msc() \
-do { \
- writel(0x00003f00, GPIO_PXFUNS(3)); \
- writel(0x00003f00, GPIO_PXSELC(3)); \
- writel(0x00003f00, GPIO_PXPES(3)); \
-} while (0)
-
-#define __gpio_get_port(p) (readl(GPIO_PXPIN(p)))
-
-#define __gpio_disable_pull(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- writel((1 << o), GPIO_PXPES(p)); \
-} while (0)
-
-#define __gpio_enable_pull(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- writel(1 << (o), GPIO_PXPEC(p)); \
-} while (0)
-
-#define __gpio_port_as_output(p, o) \
-do { \
- writel(1 << (o), GPIO_PXFUNC(p)); \
- writel(1 << (o), GPIO_PXSELC(p)); \
- writel(1 << (o), GPIO_PXDIRS(p)); \
-} while (0)
-
-#define __gpio_port_as_input(p, o) \
-do { \
- writel(1 << (o), GPIO_PXFUNC(p)); \
- writel(1 << (o), GPIO_PXSELC(p)); \
- writel(1 << (o), GPIO_PXDIRC(p)); \
-} while (0)
-
-#define __gpio_as_output(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- __gpio_port_as_output(p, o); \
-} while (0)
-
-#define __gpio_as_input(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- __gpio_port_as_input(p, o); \
-} while (0)
-
-#define __gpio_set_pin(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- writel((1 << o), GPIO_PXDATS(p)); \
-} while (0)
-
-#define __gpio_clear_pin(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- writel((1 << o), GPIO_PXDATC(p)); \
-} while (0)
-
-#define __gpio_get_pin(n) \
-({ \
- unsigned int p, o, v; \
- p = (n) / 32; \
- o = (n) % 32; \
- if (__gpio_get_port(p) & (1 << o)) \
- v = 1; \
- else \
- v = 0; \
- v; \
-})
-
-#define __gpio_as_uart0() \
-do { \
- writel(0x06000000, GPIO_PXFUNS(3)); \
- writel(0x06000000, GPIO_PXSELS(3)); \
- writel(0x06000000, GPIO_PXPES(3)); \
-} while (0)
-
-#define __gpio_jtag_to_uart0() \
-do { \
- writel(0x80000000, GPIO_PXSELS(2)); \
-} while (0)
-
-/* Clock Control Register */
-#define __cpm_get_pllm() \
- ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK) \
- >> CPM_CPPCR_PLLM_BIT)
-#define __cpm_get_plln() \
- ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK) \
- >> CPM_CPPCR_PLLN_BIT)
-#define __cpm_get_pllod() \
- ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK) \
- >> CPM_CPPCR_PLLOD_BIT)
-#define __cpm_get_hdiv() \
- ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK) \
- >> CPM_CPCCR_HDIV_BIT)
-#define __cpm_get_pdiv() \
- ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK) \
- >> CPM_CPCCR_PDIV_BIT)
-#define __cpm_get_cdiv() \
- ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK) \
- >> CPM_CPCCR_CDIV_BIT)
-#define __cpm_get_mdiv() \
- ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK) \
- >> CPM_CPCCR_MDIV_BIT)
-
-static inline unsigned int __cpm_get_pllout(void)
-{
- uint32_t m, n, no, pllout;
- uint32_t od[4] = {1, 2, 2, 4};
-
- struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- uint32_t cppcr = readl(&cpm->cppcr);
-
- if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
- m = __cpm_get_pllm() + 2;
- n = __cpm_get_plln() + 2;
- no = od[__cpm_get_pllod()];
- pllout = (CONFIG_SYS_EXTAL / (n * no)) * m;
- } else
- pllout = CONFIG_SYS_EXTAL;
-
- return pllout;
-}
-
-extern void pll_init(void);
-extern void sdram_init(void);
-extern void calc_clocks(void);
-extern void rtc_init(void);
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __JZ4740_H__ */
From 42a3f3e6ebbac4d93892d2b870502743d7308988 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Sun, 22 May 2016 11:59:50 +0800
Subject: [PATCH 09/10] mips: ath79: ar933x: Fix ethernet PHY mismatch
We need reset the Ethernet Switch analog part before operation,
or the build-in Ethernet PHY don't work.
Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
---
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 +
arch/mips/mach-ath79/reset.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index a8e51cb4cf..dabcad0d22 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -660,6 +660,7 @@
#define AR933X_RESET_GE1_MDIO BIT(23)
#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_ETH_SWITCH_ANALOG BIT(14)
#define AR933X_RESET_GE1_MAC BIT(13)
#define AR933X_RESET_WMAC BIT(11)
#define AR933X_RESET_GE0_MAC BIT(9)
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 188eccb9bf..a88bcbcfe2 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -81,7 +81,8 @@ static int eth_init_ar933x(void)
MAP_NOCACHE);
const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
- AR933X_RESET_ETH_SWITCH;
+ AR933X_RESET_ETH_SWITCH |
+ AR933X_RESET_ETH_SWITCH_ANALOG;
/* Clear MDIO slave EN bit. */
clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
From 4349b55b9953d0bb591f13ca9985edf591348ced Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Sun, 22 May 2016 11:59:49 +0800
Subject: [PATCH 10/10] mips: ath79: ar933x: Avoid warning with gcc5
GCC 5.3 report a warning: 'upper' and 'lower' may be used
uninitialized in this function [-Wmaybe-uninitialized].
Compiler might need explicit initializer.
Signed-off-by: Wills Wang <wills.wang@live.com>
---
arch/mips/mach-ath79/ar933x/ddr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 91452bcc53..7f20d34885 100644
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -268,6 +268,8 @@ void ddr_tap_tuning(void)
dir = 1;
tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
val = tap;
+ upper = tap;
+ lower = tap;
while (!done) {
err = 0;