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spi: cadence_qspi: support DM_CLK

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Support loading clk speed via DM instead of requiring ad-hoc code.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Simon Goldschmidt 2019-11-20 22:27:31 +01:00 committed by Marek Vasut
parent caaaf62ac8
commit 64c7c8c91c
2 changed files with 20 additions and 2 deletions
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21
drivers/spi/cadence_qspi.c
View File

@ -5,6 +5,7 @@
*/ */
#include <common.h> #include <common.h>
#include <clk.h>
#include <dm.h> #include <dm.h>
#include <fdtdec.h> #include <fdtdec.h>
#include <malloc.h> #include <malloc.h>
@ -24,10 +25,10 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
struct cadence_spi_priv *priv = dev_get_priv(bus); struct cadence_spi_priv *priv = dev_get_priv(bus);
cadence_qspi_apb_config_baudrate_div(priv->regbase, cadence_qspi_apb_config_baudrate_div(priv->regbase,
CONFIG_CQSPI_REF_CLK, hz); plat->ref_clk_hz, hz);
/* Reconfigure delay timing if speed is changed. */ /* Reconfigure delay timing if speed is changed. */
cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
plat->tshsl_ns, plat->tsd2d_ns, plat->tshsl_ns, plat->tsd2d_ns,
plat->tchsh_ns, plat->tslch_ns); plat->tchsh_ns, plat->tslch_ns);
@ -294,6 +295,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
{ {
struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_platdata *plat = bus->platdata;
ofnode subnode; ofnode subnode;
struct clk clk;
int ret;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0); plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
@ -325,6 +328,20 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20); plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20); plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
ret = clk_get_by_index(bus, 0, &clk);
if (ret) {
#ifdef CONFIG_CQSPI_REF_CLK
plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
#else
return ret;
#endif
} else {
plat->ref_clk_hz = clk_get_rate(&clk);
clk_free(&clk);
if (IS_ERR_VALUE(plat->ref_clk_hz))
return plat->ref_clk_hz;
}
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz, __func__, plat->regbase, plat->ahbbase, plat->max_hz,
plat->page_size); plat->page_size);

1
drivers/spi/cadence_qspi.h
View File

@ -16,6 +16,7 @@
#define CQSPI_READ_CAPTURE_MAX_DELAY 16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16
struct cadence_spi_platdata { struct cadence_spi_platdata {
unsigned int ref_clk_hz;
unsigned int max_hz; unsigned int max_hz;
void *regbase; void *regbase;
void *ahbbase; void *ahbbase;