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Add support for Cogent csb637

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Patch by Anders Larsen, 29 Apr 2005
This commit is contained in:
Wolfgang Denk 2005-10-05 02:00:09 +02:00
parent fef636b0cf
commit 645da51097
11 changed files with 766 additions and 2 deletions
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3
CHANGELOG
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@ -2,6 +2,9 @@
Changes for U-Boot 1.1.4:
======================================================================
* Add support for Cogent csb637
Patch by Anders Larsen, 29 Apr 2005
* Fix dm9161.c initialization
Patch by Anders Larsen, 29 Apr 2005

2
MAKEALL
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@ -171,7 +171,7 @@ LIST_ARM7=" \
#########################################################################
LIST_ARM9=" \
at91rm9200dk cmc_pu2 \
at91rm9200dk cmc_pu2 csb637 \
integratorap_CM920T integratorap_CM920T_ETM \
integratorap_CM922T_XA10 integratorap_CM926EJ_S \
integratorap_CM940T integratorap_CM946E_S \

3
Makefile
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@ -1390,6 +1390,9 @@ at91rm9200dk_config : unconfig
cmc_pu2_config : unconfig
@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
csb637_config : unconfig
@./mkconfig $(@:_config=) arm arm920t csb637 NULL at91rm9200
mp2usb_config : unconfig
@./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200

46
board/csb637/Makefile Normal file
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@ -0,0 +1,46 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := csb637.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

1
board/csb637/config.mk Normal file
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@ -0,0 +1 @@
TEXT_BASE = 0x23fe0000

83
board/csb637/csb637.c Normal file
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@ -0,0 +1,83 @@
/*
* (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
* Anders Larsen <alarsen@rea.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <bcm5221.h>
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* Enable Ctrlc */
console_init_f ();
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of AT91RM9200DK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = bcm5221_InitPhy;
p_phyops->IsPhyConnected = bcm5221_IsPhyConnected;
p_phyops->GetLinkSpeed = bcm5221_GetLinkSpeed;
p_phyops->AutoNegotiate = bcm5221_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

56
board/csb637/u-boot.lds Normal file
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@ -0,0 +1,56 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm920t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

3
cpu/arm920t/at91rm9200/Makefile
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@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
LIB = lib$(SOC).a
OBJS = dm9161.o ether.o i2c.o interrupts.o lxt972.o serial.o usb_ohci.o
OBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \
lxt972.o serial.o usb_ohci.o
SOBJS = lowlevel_init.o
all: .depend $(LIB)

232
cpu/arm920t/at91rm9200/bcm5221.c Normal file
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@ -0,0 +1,232 @@
/*
* Broadcom BCM5221 Ethernet PHY
*
* (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
* Anders Larsen <alarsen@rea.de>
*
* (C) Copyright 2003
* Author : Hamid Ikdoumi (Atmel)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <at91rm9200_net.h>
#include <net.h>
#include <bcm5221.h>
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/*
* Name:
* bcm5221_IsPhyConnected
* Description:
* Reads the 2 PHY ID registers
* Arguments:
* p_mac - pointer to AT91S_EMAC struct
* Return value:
* TRUE - if id read successfully
* FALSE- if error
*/
unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1);
at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2);
at91rm9200_EmacDisableMDIO (p_mac);
if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) &&
((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK)))
return TRUE;
return FALSE;
}
/*
* Name:
* bcm5221_GetLinkSpeed
* Description:
* Link parallel detection status of MAC is checked and set in the
* MAC configuration registers
* Arguments:
* p_mac - pointer to MAC
* Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac)
{
unsigned short stat1, stat2;
if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1))
return FALSE;
if (!(stat1 & BCM5221_LINK_STATUS)) /* link status up? */
return FALSE;
if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2))
return FALSE;
if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
/*set Emac for 100BaseTX and Full Duplex */
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
return TRUE;
}
if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
/*set MII for 10BaseT and Full Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_FD;
return TRUE;
}
if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
/*set MII for 100BaseTX and Half Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_SPD;
return TRUE;
}
if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
/*set MII for 10BaseT and Half Duplex */
p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
return TRUE;
}
return FALSE;
}
/*
* Name:
* bcm5221_InitPhy
* Description:
* MAC starts checking its link by using parallel detection and
* Autonegotiation and the same is set in the MAC configuration registers
* Arguments:
* p_mac - pointer to struct AT91S_EMAC
* Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac)
{
unsigned char ret = TRUE;
unsigned short IntValue;
at91rm9200_EmacEnableMDIO (p_mac);
if (!bcm5221_GetLinkSpeed (p_mac)) {
/* Try another time */
ret = bcm5221_GetLinkSpeed (p_mac);
}
/* Disable PHY Interrupts */
at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue);
/* clear FDX LED and INTR Enable */
IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE);
/* set FDX, SPD, Link, INTR masks */
IntValue |= (BCM5221_FDX_MASK | BCM5221_SPD_MASK |
BCM5221_LINK_MASK | BCM5221_INTR_MASK);
at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue);
at91rm9200_EmacDisableMDIO (p_mac);
return (ret);
}
/*
* Name:
* bcm5221_AutoNegotiate
* Description:
* MAC Autonegotiates with the partner status of same is set in the
* MAC configuration registers
* Arguments:
* dev - pointer to struct net_device
* Return value:
* TRUE - if link status set successfully
* FALSE - if link status not set
*/
unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
{
unsigned short value;
unsigned short PhyAnar;
unsigned short PhyAnalpar;
/* Set bcm5221 control register */
if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
value &= ~BCM5221_AUTONEG; /* remove autonegotiation enable */
value |= BCM5221_ISOLATE; /* Electrically isolate PHY */
if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
/* Set the Auto_negotiation Advertisement Register */
/* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX |
BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3;
if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar))
return FALSE;
/* Read the Control Register */
if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE;
if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
/* Restart Auto_negotiation */
value |= BCM5221_RESTART_AUTONEG;
value &= ~BCM5221_ISOLATE;
if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
return FALSE;
/*check AutoNegotiate complete */
udelay (10000);
at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value);
if (!(value & BCM5221_AUTONEG_COMP))
return FALSE;
/* Get the AutoNeg Link partner base page */
if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar))
return FALSE;
if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) {
/*set MII for 100BaseTX and Full Duplex */
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
return TRUE;
}
if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) {
/*set MII for 10BaseT and Full Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_FD;
return TRUE;
}
return FALSE;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

104
include/bcm5221.h Normal file
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@ -0,0 +1,104 @@
/*
* Broadcom BCM5221 Ethernet PHY
*
* (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
* Anders Larsen <alarsen@rea.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define BCM5221_BMCR 0 /* Basic Mode Control Register */
#define BCM5221_BMSR 1 /* Basic Mode Status Register */
#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */
#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */
#define BCM5221_ANAR 4 /* Auto-negotiation Advertisement Register */
#define BCM5221_ANLPAR 5 /* Auto-negotiation Link Partner Ability Register */
#define BCM5221_ANER 6 /* Auto-negotiation Expansion Register */
#define BCM5221_ACSR 24 /* Auxiliary Control/Status Register */
#define BCM5221_INTR 26 /* Interrupt Register */
/* --Bit definitions: BCM5221_BMCR */
#define BCM5221_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
#define BCM5221_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
#define BCM5221_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
#define BCM5221_AUTONEG (1 << 12)
#define BCM5221_POWER_DOWN (1 << 11)
#define BCM5221_ISOLATE (1 << 10)
#define BCM5221_RESTART_AUTONEG (1 << 9)
#define BCM5221_DUPLEX_MODE (1 << 8)
#define BCM5221_COLLISION_TEST (1 << 7)
/*--Bit definitions: BCM5221_BMSR */
#define BCM5221_100BASE_T4 (1 << 15)
#define BCM5221_100BASE_TX_FD (1 << 14)
#define BCM5221_100BASE_TX_HD (1 << 13)
#define BCM5221_10BASE_T_FD (1 << 12)
#define BCM5221_10BASE_T_HD (1 << 11)
#define BCM5221_MF_PREAMB_SUPPR (1 << 6)
#define BCM5221_AUTONEG_COMP (1 << 5)
#define BCM5221_REMOTE_FAULT (1 << 4)
#define BCM5221_AUTONEG_ABILITY (1 << 3)
#define BCM5221_LINK_STATUS (1 << 2)
#define BCM5221_JABBER_DETECT (1 << 1)
#define BCM5221_EXTEND_CAPAB (1 << 0)
/*--definitions: BCM5221_PHYID1 */
#define BCM5221_PHYID1_OUI 0x1018
#define BCM5221_LSB_MASK 0x3F
/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */
#define BCM5221_NP (1 << 15)
#define BCM5221_ACK (1 << 14)
#define BCM5221_RF (1 << 13)
#define BCM5221_FCS (1 << 10)
#define BCM5221_T4 (1 << 9)
#define BCM5221_TX_FDX (1 << 8)
#define BCM5221_TX_HDX (1 << 7)
#define BCM5221_10_FDX (1 << 6)
#define BCM5221_10_HDX (1 << 5)
#define BCM5221_AN_IEEE_802_3 0x0001
/*--Bit definitions: BCM5221_ANER */
#define BCM5221_PDF (1 << 4)
#define BCM5221_LP_NP_ABLE (1 << 3)
#define BCM5221_NP_ABLE (1 << 2)
#define BCM5221_PAGE_RX (1 << 1)
#define BCM5221_LP_AN_ABLE (1 << 0)
/*--Bit definitions: BCM5221_ACSR */
#define BCM5221_100 (1 << 1)
#define BCM5221_FDX (1 << 0)
/*--Bit definitions: BCM5221_INTR */
#define BCM5221_FDX_LED (1 << 15)
#define BCM5221_INTR_ENABLE (1 << 14)
#define BCM5221_FDX_MASK (1 << 11)
#define BCM5221_SPD_MASK (1 << 10)
#define BCM5221_LINK_MASK (1 << 9)
#define BCM5221_INTR_MASK (1 << 8)
#define BCM5221_FDX_CHG (1 << 3)
#define BCM5221_SPD_CHG (1 << 2)
#define BCM5221_LINK_CHG (1 << 1)
#define BCM5221_INTR_STATUS (1 << 0)
/****************** function prototypes **********************/
unsigned int bcm5221_IsPhyConnected(AT91PS_EMAC p_mac);
unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac);
unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac);

235
include/configs/csb637.h Normal file
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@ -0,0 +1,235 @@
/*
* (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
* Anders Larsen <alarsen@rea.de>
*
* Configuation settings for the Cogent CSB637 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */
#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define USE_920T_MMU 1
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CFG_USE_MAIN_OSCILLATOR 1
/* flash */
#define MC_PUIA_VAL 0x00000000
#define MC_PUP_VAL 0x00000000
#define MC_PUER_VAL 0x00000000
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
/* sdram */
#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define PIOC_BSR_VAL 0x00000000
#define PIOC_PDR_VAL 0xFFFF0000
#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */
#define SDRAM 0x20000000 /* address of the SDRAM */
#define SDRAM1 0x20000080 /* address of the SDRAM */
#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
#define SDRC_MR_VAL 0x00000002 /* Precharge All */
#define SDRC_MR_VAL1 0x00000004 /* refresh */
#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 38400
#define CFG_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
/*
* Hardware drivers
*/
/* define one of these to choose the DBGU, USART0 or USART1 as console */
#define CONFIG_DBGU
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_ENV_OVERWRITE 1 */
#define CONFIG_COMMANDS \
((CONFIG_CMD_DFL | \
CFG_CMD_JFFS2 | \
CFG_CMD_DHCP | \
CFG_CMD_PING ) & \
~(CFG_CMD_BDI | \
CFG_CMD_IMI | \
CFG_CMD_AUTOSCRIPT | \
CFG_CMD_FPGA | \
CFG_CMD_MISC | \
CFG_CMD_LOADS ))
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
/* the following are NOP's in our implementation */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
#define CFG_ALT_MEMTEST 1
#define CFG_MEMTEST_SCRATCH CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4
#define CONFIG_DRIVER_ETHER
#define CONFIG_NET_RETRY_COUNT 20
#undef CONFIG_AT91C_USE_RMII
#undef CONFIG_HAS_DATAFLASH
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 0
#define CFG_MAX_DATAFLASH_PAGES 16384
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
/*
* FLASH Device configuration
*/
#define PHYS_FLASH_1 0x10000000
#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
#define CFG_MAX_FLASH_SECT 64
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_FIRST_SECTOR 3
#define CFG_JFFS2_NUM_BANKS 1
#undef CFG_ENV_IS_IN_DATAFLASH
#ifdef CFG_ENV_IS_IN_DATAFLASH
#define CFG_ENV_OFFSET 0x20000
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
#else
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
#define CFG_ENV_SIZE 0x20000 /* sectors are 128K here */
#endif /* CFG_ENV_IS_IN_DATAFLASH */
#define CFG_LOAD_ADDR 0x21000000 /* default load address */
#define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 }
#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#ifndef __ASSEMBLY__
/*-----------------------------------------------------------------------
* Board specific extension for bd_info
*
* This structure is embedded in the global bd_info (bd_t) structure
* and can be used by the board specific code (eg board/...)
*/
struct bd_info_ext {
/* helper variable for board environment handling
*
* env_crc_valid == 0 => uninitialised
* env_crc_valid > 0 => environment crc in flash is valid
* env_crc_valid < 0 => environment crc in flash is invalid
*/
int env_crc_valid;
};
#endif
#define CFG_HZ 1000
#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
/* AT91C_TC_TIMER_DIV1_CLOCK */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif