imx: mx6sx: add dts for mx6sxsabreauto board
Add dts for mx6sxsabreauto board. dts related files imported fro Linux (commit e5517c2a5a4). Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
d4b1b52737
commit
6301e6570b
@ -313,6 +313,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
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imx6dl-icore-rqs.dtb \
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imx6q-icore.dtb \
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imx6q-icore-rqs.dtb \
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imx6sx-sabreauto.dtb \
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imx6ul-geam-kit.dtb
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dtb-$(CONFIG_MX7) += imx7-colibri.dtb
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1558
arch/arm/dts/imx6sx-pinfunc.h
Normal file
1558
arch/arm/dts/imx6sx-pinfunc.h
Normal file
File diff suppressed because it is too large
Load Diff
146
arch/arm/dts/imx6sx-sabreauto.dts
Normal file
146
arch/arm/dts/imx6sx-sabreauto.dts
Normal file
@ -0,0 +1,146 @@
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "imx6sx.dtsi"
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/ {
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model = "Freescale i.MX6 SoloX Sabre Auto Board";
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compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
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memory {
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reg = <0x80000000 0x80000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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vcc_sd3: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_vcc_sd3>;
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regulator-name = "VCC_SD3";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
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keep-power-in-suspend;
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wakeup-source;
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vmmc-supply = <&vcc_sd3>;
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status = "okay";
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};
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&usdhc4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4>;
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bus-width = <8>;
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cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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keep-power-in-suspend;
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wakeup-source;
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status = "okay";
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};
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&iomuxc {
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imx6x-sabreauto {
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
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MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
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MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
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MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
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MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
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MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
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MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
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MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
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MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
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MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
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MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
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MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
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MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
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fsl,pins = <
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MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
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MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
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MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
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MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
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MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
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MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
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MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
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MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
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MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
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MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
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fsl,pins = <
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MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
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MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
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MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
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MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
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MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
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MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
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MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
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MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
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MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
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MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
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>;
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};
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pinctrl_usdhc4: usdhc4grp {
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fsl,pins = <
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MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
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MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
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MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
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MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
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MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
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MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
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MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
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MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
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>;
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};
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pinctrl_vcc_sd3: vccsd3grp {
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fsl,pins = <
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MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
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>;
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};
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};
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};
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1298
arch/arm/dts/imx6sx.dtsi
Normal file
1298
arch/arm/dts/imx6sx.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,7 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_TARGET_MX6SXSABREAUTO=y
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CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
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CONFIG_BOOTDELAY=3
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CONFIG_HUSH_PARSER=y
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@ -23,6 +24,7 @@ CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_STMICRO=y
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280
include/dt-bindings/clock/imx6sx-clock.h
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280
include/dt-bindings/clock/imx6sx-clock.h
Normal file
@ -0,0 +1,280 @@
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
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#define __DT_BINDINGS_CLOCK_IMX6SX_H
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#define IMX6SX_CLK_DUMMY 0
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#define IMX6SX_CLK_CKIL 1
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#define IMX6SX_CLK_CKIH 2
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#define IMX6SX_CLK_OSC 3
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#define IMX6SX_CLK_PLL1_SYS 4
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#define IMX6SX_CLK_PLL2_BUS 5
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#define IMX6SX_CLK_PLL3_USB_OTG 6
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#define IMX6SX_CLK_PLL4_AUDIO 7
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#define IMX6SX_CLK_PLL5_VIDEO 8
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#define IMX6SX_CLK_PLL6_ENET 9
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#define IMX6SX_CLK_PLL7_USB_HOST 10
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#define IMX6SX_CLK_USBPHY1 11
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#define IMX6SX_CLK_USBPHY2 12
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#define IMX6SX_CLK_USBPHY1_GATE 13
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#define IMX6SX_CLK_USBPHY2_GATE 14
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#define IMX6SX_CLK_PCIE_REF 15
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#define IMX6SX_CLK_PCIE_REF_125M 16
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#define IMX6SX_CLK_ENET_REF 17
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#define IMX6SX_CLK_PLL2_PFD0 18
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#define IMX6SX_CLK_PLL2_PFD1 19
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#define IMX6SX_CLK_PLL2_PFD2 20
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#define IMX6SX_CLK_PLL2_PFD3 21
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#define IMX6SX_CLK_PLL3_PFD0 22
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#define IMX6SX_CLK_PLL3_PFD1 23
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#define IMX6SX_CLK_PLL3_PFD2 24
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#define IMX6SX_CLK_PLL3_PFD3 25
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#define IMX6SX_CLK_PLL2_198M 26
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#define IMX6SX_CLK_PLL3_120M 27
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#define IMX6SX_CLK_PLL3_80M 28
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#define IMX6SX_CLK_PLL3_60M 29
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#define IMX6SX_CLK_TWD 30
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#define IMX6SX_CLK_PLL4_POST_DIV 31
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#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
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#define IMX6SX_CLK_PLL5_POST_DIV 33
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#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
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#define IMX6SX_CLK_STEP 35
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#define IMX6SX_CLK_PLL1_SW 36
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#define IMX6SX_CLK_OCRAM_SEL 37
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#define IMX6SX_CLK_PERIPH_PRE 38
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#define IMX6SX_CLK_PERIPH2_PRE 39
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#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
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#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
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#define IMX6SX_CLK_PCIE_AXI_SEL 42
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#define IMX6SX_CLK_GPU_AXI_SEL 43
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#define IMX6SX_CLK_GPU_CORE_SEL 44
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#define IMX6SX_CLK_EIM_SLOW_SEL 45
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#define IMX6SX_CLK_USDHC1_SEL 46
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#define IMX6SX_CLK_USDHC2_SEL 47
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#define IMX6SX_CLK_USDHC3_SEL 48
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#define IMX6SX_CLK_USDHC4_SEL 49
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#define IMX6SX_CLK_SSI1_SEL 50
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#define IMX6SX_CLK_SSI2_SEL 51
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#define IMX6SX_CLK_SSI3_SEL 52
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#define IMX6SX_CLK_QSPI1_SEL 53
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#define IMX6SX_CLK_PERCLK_SEL 54
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#define IMX6SX_CLK_VID_SEL 55
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#define IMX6SX_CLK_ESAI_SEL 56
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#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
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#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
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#define IMX6SX_CLK_CAN_SEL 59
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#define IMX6SX_CLK_UART_SEL 60
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#define IMX6SX_CLK_QSPI2_SEL 61
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#define IMX6SX_CLK_LDB_DI1_SEL 62
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#define IMX6SX_CLK_LDB_DI0_SEL 63
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#define IMX6SX_CLK_SPDIF_SEL 64
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#define IMX6SX_CLK_AUDIO_SEL 65
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#define IMX6SX_CLK_ENET_PRE_SEL 66
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#define IMX6SX_CLK_ENET_SEL 67
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#define IMX6SX_CLK_M4_PRE_SEL 68
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#define IMX6SX_CLK_M4_SEL 69
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#define IMX6SX_CLK_ECSPI_SEL 70
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#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
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#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
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#define IMX6SX_CLK_LCDIF1_SEL 73
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#define IMX6SX_CLK_LCDIF2_SEL 74
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#define IMX6SX_CLK_DISPLAY_SEL 75
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#define IMX6SX_CLK_CSI_SEL 76
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#define IMX6SX_CLK_CKO1_SEL 77
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#define IMX6SX_CLK_CKO2_SEL 78
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#define IMX6SX_CLK_CKO 79
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#define IMX6SX_CLK_PERIPH_CLK2 80
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#define IMX6SX_CLK_PERIPH2_CLK2 81
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#define IMX6SX_CLK_IPG 82
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#define IMX6SX_CLK_GPU_CORE_PODF 83
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#define IMX6SX_CLK_GPU_AXI_PODF 84
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#define IMX6SX_CLK_LCDIF1_PODF 85
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#define IMX6SX_CLK_QSPI1_PODF 86
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#define IMX6SX_CLK_EIM_SLOW_PODF 87
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#define IMX6SX_CLK_LCDIF2_PODF 88
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#define IMX6SX_CLK_PERCLK 89
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#define IMX6SX_CLK_VID_PODF 90
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#define IMX6SX_CLK_CAN_PODF 91
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#define IMX6SX_CLK_USDHC1_PODF 92
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#define IMX6SX_CLK_USDHC2_PODF 93
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#define IMX6SX_CLK_USDHC3_PODF 94
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#define IMX6SX_CLK_USDHC4_PODF 95
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#define IMX6SX_CLK_UART_PODF 96
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#define IMX6SX_CLK_ESAI_PRED 97
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#define IMX6SX_CLK_ESAI_PODF 98
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#define IMX6SX_CLK_SSI3_PRED 99
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#define IMX6SX_CLK_SSI3_PODF 100
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#define IMX6SX_CLK_SSI1_PRED 101
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#define IMX6SX_CLK_SSI1_PODF 102
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#define IMX6SX_CLK_QSPI2_PRED 103
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#define IMX6SX_CLK_QSPI2_PODF 104
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#define IMX6SX_CLK_SSI2_PRED 105
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#define IMX6SX_CLK_SSI2_PODF 106
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#define IMX6SX_CLK_SPDIF_PRED 107
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#define IMX6SX_CLK_SPDIF_PODF 108
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#define IMX6SX_CLK_AUDIO_PRED 109
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#define IMX6SX_CLK_AUDIO_PODF 110
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#define IMX6SX_CLK_ENET_PODF 111
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#define IMX6SX_CLK_M4_PODF 112
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#define IMX6SX_CLK_ECSPI_PODF 113
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#define IMX6SX_CLK_LCDIF1_PRED 114
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#define IMX6SX_CLK_LCDIF2_PRED 115
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#define IMX6SX_CLK_DISPLAY_PODF 116
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#define IMX6SX_CLK_CSI_PODF 117
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#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
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#define IMX6SX_CLK_LDB_DI0_DIV_7 119
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#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
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#define IMX6SX_CLK_LDB_DI1_DIV_7 121
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#define IMX6SX_CLK_CKO1_PODF 122
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#define IMX6SX_CLK_CKO2_PODF 123
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#define IMX6SX_CLK_PERIPH 124
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#define IMX6SX_CLK_PERIPH2 125
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#define IMX6SX_CLK_OCRAM 126
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#define IMX6SX_CLK_AHB 127
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#define IMX6SX_CLK_MMDC_PODF 128
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#define IMX6SX_CLK_ARM 129
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#define IMX6SX_CLK_AIPS_TZ1 130
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#define IMX6SX_CLK_AIPS_TZ2 131
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#define IMX6SX_CLK_APBH_DMA 132
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#define IMX6SX_CLK_ASRC_GATE 133
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#define IMX6SX_CLK_CAAM_MEM 134
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#define IMX6SX_CLK_CAAM_ACLK 135
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#define IMX6SX_CLK_CAAM_IPG 136
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#define IMX6SX_CLK_CAN1_IPG 137
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#define IMX6SX_CLK_CAN1_SERIAL 138
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#define IMX6SX_CLK_CAN2_IPG 139
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#define IMX6SX_CLK_CAN2_SERIAL 140
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#define IMX6SX_CLK_CPU_DEBUG 141
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#define IMX6SX_CLK_DCIC1 142
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#define IMX6SX_CLK_DCIC2 143
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#define IMX6SX_CLK_AIPS_TZ3 144
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#define IMX6SX_CLK_ECSPI1 145
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#define IMX6SX_CLK_ECSPI2 146
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#define IMX6SX_CLK_ECSPI3 147
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#define IMX6SX_CLK_ECSPI4 148
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#define IMX6SX_CLK_ECSPI5 149
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#define IMX6SX_CLK_EPIT1 150
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#define IMX6SX_CLK_EPIT2 151
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#define IMX6SX_CLK_ESAI_EXTAL 152
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#define IMX6SX_CLK_WAKEUP 153
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#define IMX6SX_CLK_GPT_BUS 154
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#define IMX6SX_CLK_GPT_SERIAL 155
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#define IMX6SX_CLK_GPU 156
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#define IMX6SX_CLK_OCRAM_S 157
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#define IMX6SX_CLK_CANFD 158
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#define IMX6SX_CLK_CSI 159
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#define IMX6SX_CLK_I2C1 160
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#define IMX6SX_CLK_I2C2 161
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#define IMX6SX_CLK_I2C3 162
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#define IMX6SX_CLK_OCOTP 163
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#define IMX6SX_CLK_IOMUXC 164
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#define IMX6SX_CLK_IPMUX1 165
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#define IMX6SX_CLK_IPMUX2 166
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#define IMX6SX_CLK_IPMUX3 167
|
||||
#define IMX6SX_CLK_TZASC1 168
|
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#define IMX6SX_CLK_LCDIF_APB 169
|
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#define IMX6SX_CLK_PXP_AXI 170
|
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#define IMX6SX_CLK_M4 171
|
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#define IMX6SX_CLK_ENET 172
|
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#define IMX6SX_CLK_DISPLAY_AXI 173
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#define IMX6SX_CLK_LCDIF2_PIX 174
|
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#define IMX6SX_CLK_LCDIF1_PIX 175
|
||||
#define IMX6SX_CLK_LDB_DI0 176
|
||||
#define IMX6SX_CLK_QSPI1 177
|
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#define IMX6SX_CLK_MLB 178
|
||||
#define IMX6SX_CLK_MMDC_P0_FAST 179
|
||||
#define IMX6SX_CLK_MMDC_P0_IPG 180
|
||||
#define IMX6SX_CLK_AXI 181
|
||||
#define IMX6SX_CLK_PCIE_AXI 182
|
||||
#define IMX6SX_CLK_QSPI2 183
|
||||
#define IMX6SX_CLK_PER1_BCH 184
|
||||
#define IMX6SX_CLK_PER2_MAIN 185
|
||||
#define IMX6SX_CLK_PWM1 186
|
||||
#define IMX6SX_CLK_PWM2 187
|
||||
#define IMX6SX_CLK_PWM3 188
|
||||
#define IMX6SX_CLK_PWM4 189
|
||||
#define IMX6SX_CLK_GPMI_BCH_APB 190
|
||||
#define IMX6SX_CLK_GPMI_BCH 191
|
||||
#define IMX6SX_CLK_GPMI_IO 192
|
||||
#define IMX6SX_CLK_GPMI_APB 193
|
||||
#define IMX6SX_CLK_ROM 194
|
||||
#define IMX6SX_CLK_SDMA 195
|
||||
#define IMX6SX_CLK_SPBA 196
|
||||
#define IMX6SX_CLK_SPDIF 197
|
||||
#define IMX6SX_CLK_SSI1_IPG 198
|
||||
#define IMX6SX_CLK_SSI2_IPG 199
|
||||
#define IMX6SX_CLK_SSI3_IPG 200
|
||||
#define IMX6SX_CLK_SSI1 201
|
||||
#define IMX6SX_CLK_SSI2 202
|
||||
#define IMX6SX_CLK_SSI3 203
|
||||
#define IMX6SX_CLK_UART_IPG 204
|
||||
#define IMX6SX_CLK_UART_SERIAL 205
|
||||
#define IMX6SX_CLK_SAI1 206
|
||||
#define IMX6SX_CLK_SAI2 207
|
||||
#define IMX6SX_CLK_USBOH3 208
|
||||
#define IMX6SX_CLK_USDHC1 209
|
||||
#define IMX6SX_CLK_USDHC2 210
|
||||
#define IMX6SX_CLK_USDHC3 211
|
||||
#define IMX6SX_CLK_USDHC4 212
|
||||
#define IMX6SX_CLK_EIM_SLOW 213
|
||||
#define IMX6SX_CLK_PWM8 214
|
||||
#define IMX6SX_CLK_VADC 215
|
||||
#define IMX6SX_CLK_GIS 216
|
||||
#define IMX6SX_CLK_I2C4 217
|
||||
#define IMX6SX_CLK_PWM5 218
|
||||
#define IMX6SX_CLK_PWM6 219
|
||||
#define IMX6SX_CLK_PWM7 220
|
||||
#define IMX6SX_CLK_CKO1 221
|
||||
#define IMX6SX_CLK_CKO2 222
|
||||
#define IMX6SX_CLK_IPP_DI0 223
|
||||
#define IMX6SX_CLK_IPP_DI1 224
|
||||
#define IMX6SX_CLK_ENET_AHB 225
|
||||
#define IMX6SX_CLK_OCRAM_PODF 226
|
||||
#define IMX6SX_CLK_GPT_3M 227
|
||||
#define IMX6SX_CLK_ENET_PTP 228
|
||||
#define IMX6SX_CLK_ENET_PTP_REF 229
|
||||
#define IMX6SX_CLK_ENET2_REF 230
|
||||
#define IMX6SX_CLK_ENET2_REF_125M 231
|
||||
#define IMX6SX_CLK_AUDIO 232
|
||||
#define IMX6SX_CLK_LVDS1_SEL 233
|
||||
#define IMX6SX_CLK_LVDS1_OUT 234
|
||||
#define IMX6SX_CLK_ASRC_IPG 235
|
||||
#define IMX6SX_CLK_ASRC_MEM 236
|
||||
#define IMX6SX_CLK_SAI1_IPG 237
|
||||
#define IMX6SX_CLK_SAI2_IPG 238
|
||||
#define IMX6SX_CLK_ESAI_IPG 239
|
||||
#define IMX6SX_CLK_ESAI_MEM 240
|
||||
#define IMX6SX_CLK_LVDS1_IN 241
|
||||
#define IMX6SX_CLK_ANACLK1 242
|
||||
#define IMX6SX_PLL1_BYPASS_SRC 243
|
||||
#define IMX6SX_PLL2_BYPASS_SRC 244
|
||||
#define IMX6SX_PLL3_BYPASS_SRC 245
|
||||
#define IMX6SX_PLL4_BYPASS_SRC 246
|
||||
#define IMX6SX_PLL5_BYPASS_SRC 247
|
||||
#define IMX6SX_PLL6_BYPASS_SRC 248
|
||||
#define IMX6SX_PLL7_BYPASS_SRC 249
|
||||
#define IMX6SX_CLK_PLL1 250
|
||||
#define IMX6SX_CLK_PLL2 251
|
||||
#define IMX6SX_CLK_PLL3 252
|
||||
#define IMX6SX_CLK_PLL4 253
|
||||
#define IMX6SX_CLK_PLL5 254
|
||||
#define IMX6SX_CLK_PLL6 255
|
||||
#define IMX6SX_CLK_PLL7 256
|
||||
#define IMX6SX_PLL1_BYPASS 257
|
||||
#define IMX6SX_PLL2_BYPASS 258
|
||||
#define IMX6SX_PLL3_BYPASS 259
|
||||
#define IMX6SX_PLL4_BYPASS 260
|
||||
#define IMX6SX_PLL5_BYPASS 261
|
||||
#define IMX6SX_PLL6_BYPASS 262
|
||||
#define IMX6SX_PLL7_BYPASS 263
|
||||
#define IMX6SX_CLK_SPDIF_GCLK 264
|
||||
#define IMX6SX_CLK_CLK_END 265
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
|
||||
Loading…
Reference in New Issue
Block a user