powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shengzhou Liu
York Sun
parent
82a55c1ef8
commit
629d6b32d6
@ -50,6 +50,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_ids.o
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obj-$(CONFIG_PPC_T1042) += t1040_ids.o
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obj-$(CONFIG_PPC_T1020) += t1040_ids.o
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obj-$(CONFIG_PPC_T1022) += t1040_ids.o
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obj-$(CONFIG_PPC_T2080) += t2080_ids.o
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obj-$(CONFIG_PPC_T2081) += t2080_ids.o
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obj-$(CONFIG_QE) += qe_io.o
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@ -93,6 +95,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
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obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
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obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
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obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
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obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
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obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
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obj-y += cpu.o
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obj-y += cpu_init.o
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@ -122,7 +122,7 @@ void get_sys_info(sys_info_t *sys_info)
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sys_info->freq_processor[cpu] =
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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#ifdef CONFIG_PPC_B4860
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#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
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#define FM1_CLK_SEL 0xe0000000
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#define FM1_CLK_SHIFT 29
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#else
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142
arch/powerpc/cpu/mpc85xx/t2080_ids.c
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142
arch/powerpc/cpu/mpc85xx/t2080_ids.c
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@ -0,0 +1,142 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#ifdef CONFIG_SYS_DPAA_QBMAN
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
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/* dqrr liodn, frame data liodn, liodn off, sdest */
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SET_QP_INFO(1, 27, 1, 0),
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SET_QP_INFO(2, 28, 1, 0),
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SET_QP_INFO(3, 29, 1, 1),
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SET_QP_INFO(4, 30, 1, 1),
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SET_QP_INFO(5, 31, 1, 2),
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SET_QP_INFO(6, 32, 1, 2),
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SET_QP_INFO(7, 33, 1, 3),
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SET_QP_INFO(8, 34, 1, 3),
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SET_QP_INFO(9, 35, 1, 0),
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SET_QP_INFO(10, 36, 1, 0),
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SET_QP_INFO(11, 37, 1, 1),
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SET_QP_INFO(12, 38, 1, 1),
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SET_QP_INFO(13, 39, 1, 2),
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SET_QP_INFO(14, 40, 1, 2),
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SET_QP_INFO(15, 41, 1, 3),
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SET_QP_INFO(16, 42, 1, 3),
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SET_QP_INFO(17, 43, 1, 0),
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SET_QP_INFO(18, 44, 1, 0),
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};
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#endif
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#ifdef CONFIG_SYS_SRIO
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struct srio_liodn_id_table srio_liodn_tbl[] = {
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SET_SRIO_LIODN_BASE(1, 307),
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SET_SRIO_LIODN_BASE(2, 387),
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};
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int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
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#endif
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struct liodn_id_table liodn_tbl[] = {
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#ifdef CONFIG_SYS_DPAA_QBMAN
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SET_QMAN_LIODN(62),
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SET_BMAN_LIODN(63),
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#endif
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SET_SDHC_LIODN(1, 552),
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SET_PME_LIODN(117),
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SET_USB_LIODN(1, "fsl-usb2-mph", 553),
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SET_USB_LIODN(2, "fsl-usb2-dr", 554),
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SET_SATA_LIODN(1, 555),
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SET_SATA_LIODN(2, 556),
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
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SET_DMA_LIODN(1, 147),
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SET_DMA_LIODN(2, 227),
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SET_DMA_LIODN(3, 226),
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SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
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SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
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SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
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SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
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#ifdef CONFIG_SYS_PMAN
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SET_PMAN_LIODN(1, 513),
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SET_PMAN_LIODN(2, 514),
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SET_PMAN_LIODN(3, 515),
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#endif
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/* SET_NEXUS_LIODN(557), -- not yet implemented */
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};
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int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
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#ifdef CONFIG_SYS_DPAA_FMAN
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struct liodn_id_table fman1_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(1, 0, 88),
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SET_FMAN_RX_1G_LIODN(1, 1, 89),
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SET_FMAN_RX_1G_LIODN(1, 2, 90),
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SET_FMAN_RX_1G_LIODN(1, 3, 91),
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SET_FMAN_RX_1G_LIODN(1, 4, 92),
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SET_FMAN_RX_1G_LIODN(1, 5, 93),
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SET_FMAN_RX_10G_LIODN(1, 0, 94),
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SET_FMAN_RX_10G_LIODN(1, 1, 95),
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};
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int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
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#endif
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struct liodn_id_table sec_liodn_tbl[] = {
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SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
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SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
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SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
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SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
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SET_SEC_RTIC_LIODN_ENTRY(a, 453),
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SET_SEC_RTIC_LIODN_ENTRY(b, 549),
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SET_SEC_RTIC_LIODN_ENTRY(c, 550),
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SET_SEC_RTIC_LIODN_ENTRY(d, 551),
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SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
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SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
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SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
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SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
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SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
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SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
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SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
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SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
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};
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int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
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#ifdef CONFIG_SYS_DPAA_RMAN
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struct liodn_id_table rman_liodn_tbl[] = {
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/* Set RMan block 0-3 liodn offset */
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SET_RMAN_LIODN(0, 6),
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SET_RMAN_LIODN(1, 7),
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SET_RMAN_LIODN(2, 8),
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SET_RMAN_LIODN(3, 9),
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};
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int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
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#endif
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struct liodn_id_table liodn_bases[] = {
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#ifdef CONFIG_SYS_DPAA_DCE
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[FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694),
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#endif
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[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
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#ifdef CONFIG_SYS_DPAA_FMAN
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[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
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#endif
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#ifdef CONFIG_SYS_DPAA_RMAN
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[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
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#endif
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};
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208
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
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208
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
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@ -0,0 +1,208 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include "fsl_corenet2_serdes.h"
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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static const struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
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{0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
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PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
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{0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
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PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
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{0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
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{0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE1,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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#if defined(CONFIG_PPC_T2080)
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{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM1_MAC1, XFI_FM1_MAC2,
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PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
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SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM1_MAC1, XFI_FM1_MAC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
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PCIE3, PCIE3, PCIE3, PCIE3} },
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{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
|
||||
XFI_FM1_MAC1, XFI_FM1_MAC2,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
|
||||
#elif defined(CONFIG_PPC_T2081)
|
||||
{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
#endif
|
||||
{}
|
||||
};
|
||||
|
||||
#ifndef CONFIG_PPC_T2081
|
||||
static const struct serdes_config serdes2_cfg_tbl[] = {
|
||||
/* SerDes 2 */
|
||||
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
|
||||
{0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
|
||||
{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
|
||||
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
|
||||
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
|
||||
{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
|
||||
{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
|
||||
{}
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct serdes_config *serdes_cfg_tbl[] = {
|
||||
serdes1_cfg_tbl,
|
||||
#ifndef CONFIG_PPC_T2081
|
||||
serdes2_cfg_tbl,
|
||||
#endif
|
||||
};
|
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
{
|
||||
const struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
ptr = serdes_cfg_tbl[serdes];
|
||||
while (ptr->protocol) {
|
||||
if (ptr->protocol == cfg)
|
||||
return ptr->lanes[lane];
|
||||
ptr++;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
||||
{
|
||||
int i;
|
||||
const struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
ptr = serdes_cfg_tbl[serdes];
|
||||
while (ptr->protocol) {
|
||||
if (ptr->protocol == prtcl)
|
||||
break;
|
||||
ptr++;
|
||||
}
|
||||
|
||||
if (!ptr->protocol)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (ptr->lanes[i] != NONE)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -75,6 +75,8 @@ static struct cpu_type cpu_type_list[] = {
|
||||
CPU_TYPE_ENTRY(T1020, T1020, 0),
|
||||
CPU_TYPE_ENTRY(T1021, T1021, 0),
|
||||
CPU_TYPE_ENTRY(T1022, T1022, 0),
|
||||
CPU_TYPE_ENTRY(T2080, T2080, 0),
|
||||
CPU_TYPE_ENTRY(T2081, T2081, 0),
|
||||
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
|
||||
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
|
||||
CPU_TYPE_ENTRY(BSC9132, 9132, 2),
|
||||
|
||||
@ -718,6 +718,50 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define CONFIG_E6500
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_QMAN_V3
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
||||
#if defined(CONFIG_PPC_T2080)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 4
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_FSL_SRIO_LIODN
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#elif defined(CONFIG_PPC_T2081)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_PME_PLAT_CLK_DIV 1
|
||||
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
|
||||
#define CONFIG_SYS_FM1_CLK 0
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
#define CONFIG_SYS_FSL_ISBC_VER 2
|
||||
|
||||
#elif defined(CONFIG_PPC_C29X)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
|
||||
@ -1759,6 +1759,12 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
|
||||
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
|
||||
#endif
|
||||
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
|
||||
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
|
||||
@ -1821,6 +1827,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
|
||||
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
|
||||
#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
|
||||
#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
|
||||
#endif
|
||||
u8 res18[192];
|
||||
u32 scratchrw[4]; /* Scratch Read/Write */
|
||||
@ -2818,6 +2833,7 @@ struct ccsr_pman {
|
||||
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
|
||||
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
|
||||
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
|
||||
#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
|
||||
#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
|
||||
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
|
||||
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
|
||||
|
||||
@ -1127,6 +1127,8 @@
|
||||
#define SVR_T1020 0x852100
|
||||
#define SVR_T1021 0x852101
|
||||
#define SVR_T1022 0x852102
|
||||
#define SVR_T2080 0x853000
|
||||
#define SVR_T2081 0x853100
|
||||
|
||||
#define SVR_8610 0x80A000
|
||||
#define SVR_8641 0x809000
|
||||
|
||||
@ -28,6 +28,8 @@ obj-$(CONFIG_PPC_T1040) += t1040.o
|
||||
obj-$(CONFIG_PPC_T1042) += t1040.o
|
||||
obj-$(CONFIG_PPC_T1020) += t1040.o
|
||||
obj-$(CONFIG_PPC_T1022) += t1040.o
|
||||
obj-$(CONFIG_PPC_T2080) += t2080.o
|
||||
obj-$(CONFIG_PPC_T2081) += t2080.o
|
||||
obj-$(CONFIG_PPC_T4240) += t4240.o
|
||||
obj-$(CONFIG_PPC_T4160) += t4240.o
|
||||
obj-$(CONFIG_PPC_B4420) += b4860.o
|
||||
|
||||
91
drivers/net/fm/t2080.c
Normal file
91
drivers/net/fm/t2080.c
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <phy.h>
|
||||
#include <fm_eth.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
u32 port_to_devdisr[] = {
|
||||
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
|
||||
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
|
||||
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
|
||||
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
|
||||
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
|
||||
[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
|
||||
[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
|
||||
[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
|
||||
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
|
||||
[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
|
||||
[FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
|
||||
[FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
|
||||
};
|
||||
|
||||
static int is_device_disabled(enum fm_port port)
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 devdisr2 = in_be32(&gur->devdisr2);
|
||||
|
||||
return port_to_devdisr[port] & devdisr2;
|
||||
}
|
||||
|
||||
void fman_disable_port(enum fm_port port)
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
|
||||
}
|
||||
|
||||
phy_interface_t fman_port_enet_if(enum fm_port port)
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
|
||||
|
||||
if (is_device_disabled(port))
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
|
||||
if ((port == FM1_10GEC1 || port == FM1_10GEC2 ||
|
||||
port == FM1_10GEC3 || port == FM1_10GEC4) &&
|
||||
((is_serdes_configured(XAUI_FM1_MAC9)) ||
|
||||
(is_serdes_configured(XFI_FM1_MAC1)) ||
|
||||
(is_serdes_configured(XFI_FM1_MAC2)) ||
|
||||
(is_serdes_configured(XFI_FM1_MAC9)) ||
|
||||
(is_serdes_configured(XFI_FM1_MAC10))))
|
||||
return PHY_INTERFACE_MODE_XGMII;
|
||||
|
||||
if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
|
||||
FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
|
||||
FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
|
||||
FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
switch (port) {
|
||||
case FM1_DTSEC1:
|
||||
case FM1_DTSEC2:
|
||||
case FM1_DTSEC3:
|
||||
case FM1_DTSEC4:
|
||||
case FM1_DTSEC5:
|
||||
case FM1_DTSEC6:
|
||||
case FM1_DTSEC9:
|
||||
case FM1_DTSEC10:
|
||||
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
|
||||
return PHY_INTERFACE_MODE_SGMII;
|
||||
break;
|
||||
default:
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
}
|
||||
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user