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keystone2: use EFUSE_BOOTROM information to configure PLLs

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This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This commit is contained in:
Vitaly Andrianov 2014-07-25 22:23:19 +03:00 committed by Tom Rini
parent 9352697aa0
commit 61f66fd5a8
9 changed files with 174 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/cpu/armv7/keystone/clock-k2e.c
View File

@ -17,6 +17,22 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};
int dev_speeds[] = {
SPD800,
SPD850,
SPD1000,
SPD1250,
SPD1350,
SPD1400,
SPD1500,
SPD1400,
SPD1350,
SPD1250,
SPD1000,
SPD850,
SPD800
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD

32
arch/arm/cpu/armv7/keystone/clock-k2hk.c
View File

@ -19,6 +19,38 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
int dev_speeds[] = {
SPD800,
SPD1000,
SPD1200,
SPD800,
SPD800,
SPD800,
SPD800,
SPD800,
SPD1200,
SPD1000,
SPD800,
SPD800,
SPD800,
};
int arm_speeds[] = {
SPD800,
SPD1000,
SPD1200,
SPD1350,
SPD1400,
SPD800,
SPD1400,
SPD1350,
SPD1200,
SPD1000,
SPD800,
SPD800,
SPD800,
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD

43
arch/arm/cpu/armv7/keystone/clock.c
View File

@ -11,6 +11,8 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
#define MAX_SPEEDS 13
static void wait_for_completion(const struct pll_init_data *data)
{
int i;
@ -218,3 +220,44 @@ void init_plls(int num_pll, struct pll_init_data *config)
for (i = 0; i < num_pll; i++)
init_pll(&config[i]);
}
static int get_max_speed(u32 val, int *speeds)
{
int j;
if (!val)
return speeds[0];
for (j = 1; j < MAX_SPEEDS; j++) {
if (val == 1)
return speeds[j];
val >>= 1;
}
return SPD800;
}
#ifdef CONFIG_SOC_K2HK
static u32 read_efuse_bootrom(void)
{
return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
__raw_readl(KS2_REV1_DEVSPEED);
}
#else
static inline u32 read_efuse_bootrom(void)
{
return __raw_readl(KS2_EFUSE_BOOTROM);
}
#endif
inline int get_max_dev_speed(void)
{
return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
}
#ifndef CONFIG_SOC_K2E
inline int get_max_arm_speed(void)
{
return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
}
#endif

16
arch/arm/include/asm/arch-keystone/clock-k2e.h
View File

@ -56,10 +56,26 @@ enum pll_type_e {
DDR3_PLL,
};
enum {
SPD800,
SPD850,
SPD1000,
SPD1250,
SPD1350,
SPD1400,
SPD1500,
SPD_RSV
};
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2}
#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2}
#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2}
#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}

14
arch/arm/include/asm/arch-keystone/clock-k2hk.h
View File

@ -63,21 +63,35 @@ enum pll_type_e {
DDR3B_PLL,
};
enum {
SPD800,
SPD1000,
SPD1200,
SPD1350,
SPD1400,
SPD_RSV
};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_999 {CORE_PLL, 122, 15, 1}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
#define CORE_PLL_1200 {CORE_PLL, 625, 32, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
#define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1}
#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
#define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1}
#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
#define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1}
#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}

4
arch/arm/include/asm/arch-keystone/clock.h
View File

@ -38,12 +38,16 @@ struct pll_init_data {
};
extern const struct keystone_pll_regs keystone_pll_regs[];
extern int dev_speeds[];
extern int arm_speeds[];
void init_plls(int num_pll, struct pll_init_data *config);
void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
int get_max_dev_speed(void);
int get_max_arm_speed(void);
#endif
#endif

4
arch/arm/include/asm/arch-keystone/hardware.h
View File

@ -138,6 +138,10 @@ typedef volatile unsigned int *dv_reg_p;
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define DBG_LEAVE_DSPS_ON 0x1
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
/* Queue manager */
#define KS2_QM_MANAGER_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000

23
board/ti/ks2_evm/board_k2e.c
View File

@ -25,15 +25,30 @@ unsigned int external_clk[ext_clk_count] = {
[usb_clk] = 100000000,
};
static struct pll_init_data pll_config[] = {
CORE_PLL_1200,
PASS_PLL_1000,
static struct pll_init_data core_pll_config[] = {
CORE_PLL_800,
CORE_PLL_850,
CORE_PLL_1000,
CORE_PLL_1250,
CORE_PLL_1350,
CORE_PLL_1400,
CORE_PLL_1500,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_1000;
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
init_plls(ARRAY_SIZE(pll_config), pll_config);
int speed;
speed = get_max_dev_speed();
init_pll(&core_pll_config[speed]);
init_pll(&pa_pll_config);
return 0;
}
#endif

31
board/ti/ks2_evm/board_k2hk.c
View File

@ -8,6 +8,7 @@
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emac_defs.h>
@ -28,12 +29,23 @@ unsigned int external_clk[ext_clk_count] = {
[rp1_clk] = 123456789
};
static struct pll_init_data pll_config[] = {
CORE_PLL_1228,
PASS_PLL_983,
TETRIS_PLL_1200,
static struct pll_init_data core_pll_config[] = {
CORE_PLL_799,
CORE_PLL_999,
CORE_PLL_1200,
};
static struct pll_init_data tetris_pll_config[] = {
TETRIS_PLL_800,
TETRIS_PLL_1000,
TETRIS_PLL_1200,
TETRIS_PLL_1350,
TETRIS_PLL_1400,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
@ -75,7 +87,16 @@ int get_num_eth_ports(void)
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
init_plls(ARRAY_SIZE(pll_config), pll_config);
int speed;
speed = get_max_dev_speed();
init_pll(&core_pll_config[speed]);
init_pll(&pa_pll_config);
speed = get_max_arm_speed();
init_pll(&tetris_pll_config[speed]);
return 0;
}
#endif