Convert CONFIG_FSL_MEMAC et al to Kconfig

This converts the following to Kconfig:
   CONFIG_FSL_MEMAC
   CONFIG_SYS_MEMAC_LITTLE_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-07-23 13:05:10 -04:00
parent 923a855509
commit 612f7a61d5
44 changed files with 77 additions and 23 deletions

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@ -40,8 +40,6 @@
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06100000
@ -49,8 +47,6 @@
/* SMMU Defintions */
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DCFG - GUR */
/* Cache Coherent Interconnect */
#define CCI_MN_BASE 0x04000000
#define CCI_MN_RNF_NODEID_LIST 0x180
@ -134,8 +130,6 @@
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* DCFG - GUR */
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@ -165,8 +159,6 @@
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06200000
@ -214,8 +206,6 @@
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* SEC */
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1

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@ -89,6 +89,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -108,6 +108,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y

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@ -78,6 +78,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y

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@ -81,6 +81,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y

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@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y

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@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y

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@ -77,6 +77,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y

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@ -83,6 +83,8 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y

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@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -97,6 +97,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -77,6 +77,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -91,6 +91,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y

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@ -80,6 +80,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x580980000
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME_PCI=y

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@ -83,6 +83,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x580980000
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME_PCI=y

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@ -102,6 +102,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME_PCI=y

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@ -72,6 +72,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME_PCI=y

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@ -95,6 +95,8 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y

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@ -71,6 +71,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -78,6 +78,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -86,6 +86,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -94,6 +94,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -82,6 +82,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y

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@ -89,6 +89,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y

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@ -75,6 +75,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -84,6 +84,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -84,6 +84,8 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -84,6 +84,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y

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@ -92,6 +92,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y

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@ -93,6 +93,8 @@ CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_MEMAC=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y

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@ -71,6 +71,7 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -375,6 +375,7 @@ config SYS_QE_FMAN_FW_LENGTH
config SYS_FMAN_V3
bool
select FSL_MEMAC
help
SoC has FMan v3 with mEMAC

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@ -11,7 +11,6 @@ obj-y += tgec.o
obj-y += tgec_phy.o
# Soc have FMAN v3 with mEMAC
obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
obj-$(CONFIG_SYS_FMAN_V3) += memac.o
# SoC specific SERDES support

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@ -345,6 +345,13 @@ config PHY_NCSI
endif #PHYLIB
config FSL_MEMAC
bool "NXP mEMAC PHY support"
config SYS_MEMAC_LITTLE_ENDIAN
bool "mEMAC is access in little endian mode"
depends on FSL_MEMAC || FSL_LS_MDIO
config PHY_RESET_DELAY
int "Extra delay after reset before MII register access"
default 0

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@ -297,8 +297,6 @@
#endif
#endif
#define CONFIG_FSL_MEMAC
#define COMMON_ENV \
"kernelheader_addr_r=0x80200000\0" \
"fdtheader_addr_r=0x80100000\0" \
@ -467,7 +465,6 @@
#endif
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C

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@ -202,8 +202,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_FSL_MEMAC
#ifndef SPL_NO_ENV
/* Initial environment variables */
#ifdef CONFIG_TFABOOT

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@ -239,8 +239,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_FSL_MEMAC
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC
@ -385,7 +383,6 @@
#endif
#if defined(CONFIG_FSL_MC_ENET)
#define CONFIG_FSL_MEMAC
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E

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@ -226,8 +226,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_FSL_MEMAC
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \

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@ -10,8 +10,6 @@
#include <asm/arch/config.h>
#include <asm/arch/soc.h>
#define CONFIG_FSL_MEMAC
#define CONFIG_SYS_FLASH_BASE 0x20000000
/* DDR */