Convert CONFIG_FSL_MEMAC et al to Kconfig
This converts the following to Kconfig: CONFIG_FSL_MEMAC CONFIG_SYS_MEMAC_LITTLE_ENDIAN Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
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923a855509
commit
612f7a61d5
@ -40,8 +40,6 @@
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06100000
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@ -49,8 +47,6 @@
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/* SMMU Defintions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DCFG - GUR */
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/* Cache Coherent Interconnect */
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#define CCI_MN_BASE 0x04000000
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#define CCI_MN_RNF_NODEID_LIST 0x180
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@ -134,8 +130,6 @@
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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@ -165,8 +159,6 @@
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06200000
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@ -214,8 +206,6 @@
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* SEC */
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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@ -89,6 +89,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -108,6 +108,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_MDIO_MUX=y
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@ -78,6 +78,8 @@ CONFIG_SPI_FLASH_SPANSION=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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@ -81,6 +81,8 @@ CONFIG_SPI_FLASH_SPANSION=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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@ -77,6 +77,8 @@ CONFIG_SPI_FLASH_SPANSION=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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@ -83,6 +83,8 @@ CONFIG_SPI_FLASH_SPANSION=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -97,6 +97,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -77,6 +77,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -91,6 +91,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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@ -80,6 +80,8 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_CORTINA_FW_ADDR=0x580980000
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_NVME_PCI=y
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@ -83,6 +83,8 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_CORTINA_FW_ADDR=0x580980000
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_NVME_PCI=y
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@ -102,6 +102,8 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_CORTINA_FW_ADDR=0x980000
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_NVME_PCI=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_CORTINA_FW_ADDR=0x980000
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_NVME_PCI=y
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@ -95,6 +95,8 @@ CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_MDIO_MUX=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_CORTINA_FW_ADDR=0x980000
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -78,6 +78,8 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_CORTINA_FW_ADDR=0x980000
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -86,6 +86,8 @@ CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -94,6 +94,8 @@ CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -82,6 +82,8 @@ CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_MDIO_MUX=y
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@ -89,6 +89,8 @@ CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_MDIO_MUX=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -84,6 +84,8 @@ CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_MDIO_MUX=y
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@ -92,6 +92,8 @@ CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_MDIO_MUX=y
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@ -93,6 +93,8 @@ CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_VITESSE=y
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CONFIG_FSL_MEMAC=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_MDIO_MUX=y
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@ -71,6 +71,7 @@ CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_VITESSE=y
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CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -375,6 +375,7 @@ config SYS_QE_FMAN_FW_LENGTH
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config SYS_FMAN_V3
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bool
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select FSL_MEMAC
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help
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SoC has FMan v3 with mEMAC
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@ -11,7 +11,6 @@ obj-y += tgec.o
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obj-y += tgec_phy.o
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# Soc have FMAN v3 with mEMAC
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obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
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obj-$(CONFIG_SYS_FMAN_V3) += memac.o
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# SoC specific SERDES support
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@ -345,6 +345,13 @@ config PHY_NCSI
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endif #PHYLIB
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config FSL_MEMAC
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bool "NXP mEMAC PHY support"
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config SYS_MEMAC_LITTLE_ENDIAN
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bool "mEMAC is access in little endian mode"
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depends on FSL_MEMAC || FSL_LS_MDIO
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config PHY_RESET_DELAY
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int "Extra delay after reset before MII register access"
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default 0
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#endif
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#endif
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#define CONFIG_FSL_MEMAC
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#define COMMON_ENV \
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"kernelheader_addr_r=0x80200000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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@ -467,7 +465,6 @@
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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#define CONFIG_FSL_MEMAC
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#define RGMII_PHY1_ADDR 0x1
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#define RGMII_PHY2_ADDR 0x2
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#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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||||
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||||
#define CONFIG_FSL_MEMAC
|
||||
|
||||
#ifndef SPL_NO_ENV
|
||||
/* Initial environment variables */
|
||||
#ifdef CONFIG_TFABOOT
|
||||
|
@ -239,8 +239,6 @@
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
|
||||
#define CONFIG_FSL_MEMAC
|
||||
|
||||
/* Initial environment variables */
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
#ifdef CONFIG_NXP_ESBC
|
||||
@ -385,7 +383,6 @@
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
#define CONFIG_FSL_MEMAC
|
||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
|
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
||||
|
@ -226,8 +226,6 @@
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
|
||||
#define CONFIG_FSL_MEMAC
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(USB, usb, 0) \
|
||||
func(MMC, mmc, 0) \
|
||||
|
@ -10,8 +10,6 @@
|
||||
#include <asm/arch/config.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#define CONFIG_FSL_MEMAC
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000
|
||||
|
||||
/* DDR */
|
||||
|
Loading…
Reference in New Issue
Block a user