Move CONFIG_FSL_ESDHC to defconfig
Moved CONFIG_FSL_ESDHC from header files to defconfig files. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
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@ -35,6 +35,7 @@ CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_IMX_LPI2C=y
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CONFIG_MISC=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_MICREL=y
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@ -34,6 +34,7 @@ CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_IMX_LPI2C=y
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CONFIG_MISC=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_MICREL=y
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@ -30,6 +30,7 @@ CONFIG_DM_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_MXC=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_DM_ETH=y
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CONFIG_PINCTRL=y
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@ -51,6 +51,7 @@ CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_MISC=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_ATHEROS=y
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@ -55,6 +55,7 @@ CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_MISC=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ADDR_ENABLE=y
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@ -34,6 +34,7 @@ CONFIG_CMD_EXT4_WRITE=y
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# CONFIG_ISO_PARTITION is not set
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# CONFIG_EFI_PARTITION is not set
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_FEC_MXC=y
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@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_SATA_CEVA=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_SATA_CEVA=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_WINBOND=y
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@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_SATA_CEVA=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_SATA_CEVA=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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@ -32,6 +32,7 @@ CONFIG_DM=y
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CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -35,6 +35,7 @@ CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_FSL_CAAM=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -32,6 +32,7 @@ CONFIG_DM=y
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CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -35,6 +35,7 @@ CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_FSL_CAAM=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -15,7 +15,6 @@
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#undef CONFIG_BOOTM_NETBSD
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define USDHC1_BASE_ADDR 0x5b010000
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@ -15,7 +15,6 @@
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#undef CONFIG_BOOTM_NETBSD
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define USDHC1_BASE_ADDR 0x5b010000
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@ -216,7 +216,6 @@
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#define CONFIG_IMX_BOOTAUX
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#define CONFIG_CMD_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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@ -47,7 +47,6 @@
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#undef CONFIG_CMD_CRC32
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#undef CONFIG_BOOTM_NETBSD
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define USDHC1_BASE_ADDR 0x5B010000
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@ -46,7 +46,6 @@
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#undef CONFIG_CMD_CRC32
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#undef CONFIG_BOOTM_NETBSD
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define USDHC1_BASE_ADDR 0x5B010000
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@ -39,7 +39,6 @@
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#define CONFIG_SYS_I2C_SPEED 100000
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/* MMC Configs */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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@ -41,7 +41,6 @@
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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@ -164,7 +164,6 @@
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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@ -178,12 +177,6 @@
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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#define I2C_MUX_CH_DEFAULT 0x8
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