avr32: Enable SPI flash support on ATNGW100
The ATNGW100 has 8MB DataFlash on board. Give users access to it through the new SPI flash framework. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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@ -60,6 +60,9 @@ int board_early_init_f(void)
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#if defined(CONFIG_MMC)
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gpio_enable_mmci();
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#endif
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#if defined(CONFIG_ATMEL_SPI)
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gpio_enable_spi0(1 << 0);
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#endif
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return 0;
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}
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@ -89,3 +92,25 @@ void board_init_info(void)
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gd->bd->bi_phy_id[0] = 0x01;
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gd->bd->bi_phy_id[1] = 0x03;
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}
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#include <spi.h>
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#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA3
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
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}
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#endif /* CONFIG_ATMEL_SPI */
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@ -114,6 +114,8 @@
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#undef CONFIG_CMD_AUTOSCRIPT
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#undef CONFIG_CMD_FPGA
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@ -126,6 +128,10 @@
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#define CFG_NR_PIOS 5
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#define CFG_HSDRAMC 1
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#define CONFIG_MMC 1
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#define CONFIG_ATMEL_SPI 1
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#define CONFIG_SPI_FLASH 1
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#define CONFIG_SPI_FLASH_ATMEL 1
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#define CFG_DCACHE_LINESZ 32
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#define CFG_ICACHE_LINESZ 32
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