ddr: altera: sequencer: Clean data types
Replace uintNN_t with uNN. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Marek Vasut
parent
96fd4362cf
commit
5ded7320c8
@ -60,7 +60,7 @@ const struct socfpga_sdram_misc_config *misccfg;
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STATIC_SKIP_DELAY_LOOPS)
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/* calibration steps requested by the rtl */
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uint16_t dyn_calib_steps;
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u16 dyn_calib_steps;
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/*
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* To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
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@ -71,7 +71,7 @@ uint16_t dyn_calib_steps;
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* zero when skipping
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*/
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uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
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u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
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#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
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((non_skip_value) & skip_delay_mask)
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@ -79,8 +79,8 @@ uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
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struct gbl_type *gbl;
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struct param_type *param;
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static void set_failing_group_stage(uint32_t group, uint32_t stage,
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uint32_t substage)
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static void set_failing_group_stage(u32 group, u32 stage,
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u32 substage)
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{
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/*
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* Only set the global stage if there was not been any other
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@ -286,49 +286,49 @@ static void scc_mgr_initialize(void)
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}
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}
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static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
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static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase)
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{
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scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
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}
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static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
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static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay)
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{
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scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
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}
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static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
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static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase)
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{
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scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
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}
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static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
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static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
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{
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scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
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}
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static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
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static void scc_mgr_set_dqs_io_in_delay(u32 delay)
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{
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scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
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delay);
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}
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static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
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static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
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{
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scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
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}
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static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
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static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
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{
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scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
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}
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static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
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static void scc_mgr_set_dqs_out1_delay(u32 delay)
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{
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scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
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delay);
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}
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static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
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static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay)
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{
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scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
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rwcfg->mem_dq_per_write_dqs + 1 + dm,
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@ -336,7 +336,7 @@ static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
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}
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/* load up dqs config settings */
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static void scc_mgr_load_dqs(uint32_t dqs)
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static void scc_mgr_load_dqs(u32 dqs)
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{
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writel(dqs, &sdr_scc_mgr->dqs_ena);
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}
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@ -348,13 +348,13 @@ static void scc_mgr_load_dqs_io(void)
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}
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/* load up dq config settings */
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static void scc_mgr_load_dq(uint32_t dq_in_group)
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static void scc_mgr_load_dq(u32 dq_in_group)
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{
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writel(dq_in_group, &sdr_scc_mgr->dq_ena);
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}
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/* load up dm config settings */
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static void scc_mgr_load_dm(uint32_t dm)
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static void scc_mgr_load_dm(u32 dm)
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{
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writel(dm, &sdr_scc_mgr->dm_ena);
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}
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@ -399,8 +399,8 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
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read_group, phase, 0);
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}
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static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
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uint32_t phase)
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static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group,
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u32 phase)
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{
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/*
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* USER although the h/w doesn't support different phases per
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@ -414,8 +414,8 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
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write_group, phase, 0);
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}
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static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
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uint32_t delay)
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static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group,
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u32 delay)
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{
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/*
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* In shadow register mode, the T11 settings are stored in
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@ -615,9 +615,9 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only)
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* apply and load a particular input delay for the DQ pins in a group
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* group_bgn is the index of the first dq pin (in the write group)
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*/
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static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
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static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay)
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{
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uint32_t i, p;
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u32 i, p;
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for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) {
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scc_mgr_set_dq_in_delay(p, delay);
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@ -642,9 +642,9 @@ static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
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}
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/* apply and load a particular output delay for the DM pins in a group */
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static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
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static void scc_mgr_apply_group_dm_out1_delay(u32 delay1)
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{
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uint32_t i;
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u32 i;
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for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
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scc_mgr_set_dm_out1_delay(i, delay1);
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@ -654,8 +654,8 @@ static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
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/* apply and load delay on both DQS and OCT out1 */
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static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
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uint32_t delay)
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static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group,
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u32 delay)
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{
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scc_mgr_set_dqs_out1_delay(delay);
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scc_mgr_load_dqs_io();
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@ -840,7 +840,7 @@ static void delay_for_n_mem_clocks(const u32 clocks)
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*/
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static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
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{
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uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
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u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
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RW_MGR_RUN_SINGLE_GROUP_OFFSET;
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/* Load counters */
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@ -2147,7 +2147,7 @@ static int search_right_edge(const int write, const int rank_bgn,
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} else { /* READ-ONLY */
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scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
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if (iocfg->shift_dqs_en_when_shift_dqs) {
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uint32_t delay = d + start_dqs_en;
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u32 delay = d + start_dqs_en;
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if (delay > iocfg->dqs_en_delay_max)
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delay = iocfg->dqs_en_delay_max;
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scc_mgr_set_dqs_en_delay(read_group, delay);
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@ -2381,7 +2381,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
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* Store these as signed since there are comparisons with
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* signed numbers.
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*/
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uint32_t sticky_bit_chk;
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u32 sticky_bit_chk;
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int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
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int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
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int32_t orig_mid_min, mid_min;
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@ -2665,9 +2665,9 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
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*/
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static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
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{
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uint32_t p, d;
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uint32_t dtaps_per_ptap;
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uint32_t failed_substage;
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u32 p, d;
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u32 dtaps_per_ptap;
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u32 failed_substage;
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int ret;
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@ -2783,7 +2783,7 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
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* detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
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* Calibrate LFIFO to find smallest read latency.
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*/
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static uint32_t rw_mgr_mem_calibrate_lfifo(void)
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static u32 rw_mgr_mem_calibrate_lfifo(void)
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{
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int found_one = 0;
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@ -3193,8 +3193,8 @@ static void mem_init_latency(void)
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*/
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static void mem_skip_calibrate(void)
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{
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uint32_t vfifo_offset;
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uint32_t i, j, r;
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u32 vfifo_offset;
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u32 i, j, r;
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debug("%s:%d\n", __func__, __LINE__);
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/* Need to update every shadow register set used by the interface */
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@ -3279,15 +3279,15 @@ static void mem_skip_calibrate(void)
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*
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* Perform memory calibration.
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*/
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static uint32_t mem_calibrate(void)
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static u32 mem_calibrate(void)
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{
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uint32_t i;
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uint32_t rank_bgn, sr;
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uint32_t write_group, write_test_bgn;
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uint32_t read_group, read_test_bgn;
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uint32_t run_groups, current_run;
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uint32_t failing_groups = 0;
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uint32_t group_failed = 0;
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u32 i;
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u32 rank_bgn, sr;
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u32 write_group, write_test_bgn;
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u32 read_group, read_test_bgn;
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u32 run_groups, current_run;
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u32 failing_groups = 0;
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u32 group_failed = 0;
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const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width /
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rwcfg->mem_if_write_dqs_width;
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@ -3506,7 +3506,7 @@ static int run_mem_calibrate(void)
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*/
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static void debug_mem_calibrate(int pass)
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{
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uint32_t debug_info;
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u32 debug_info;
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if (pass) {
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printf("%s: CALIBRATION PASSED\n", __FILE__);
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@ -3594,13 +3594,13 @@ static void initialize_reg_file(void)
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*/
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static void initialize_hps_phy(void)
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{
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uint32_t reg;
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u32 reg;
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/*
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* Tracking also gets configured here because it's in the
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* same register.
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*/
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uint32_t trk_sample_count = 7500;
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uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
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u32 trk_sample_count = 7500;
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u32 trk_long_idle_sample_count = (10 << 16) | 100;
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/*
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* Format is number of outer loops in the 16 MSB, sample
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* count in 16 LSB.
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@ -3684,7 +3684,7 @@ int sdram_calibration_full(void)
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{
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struct param_type my_param;
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struct gbl_type my_gbl;
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uint32_t pass;
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u32 pass;
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memset(&my_param, 0, sizeof(my_param));
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memset(&my_gbl, 0, sizeof(my_gbl));
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