Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
This commit is contained in:
commit
5dd372a23d
13
Makefile
13
Makefile
@ -309,26 +309,25 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin
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$(obj)u-boot.dis: $(obj)u-boot
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$(obj)u-boot.dis: $(obj)u-boot
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$(OBJDUMP) -d $< > $@
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$(OBJDUMP) -d $< > $@
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$(obj)u-boot: depend $(obj)include/autoconf.mk \
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$(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
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$(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
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UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
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UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
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cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
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cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
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--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
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--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
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-Map u-boot.map -o u-boot
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-Map u-boot.map -o u-boot
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$(OBJS):
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$(OBJS): $(obj)include/autoconf.mk
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$(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
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$(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
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$(LIBS):
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$(LIBS): $(obj)include/autoconf.mk
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$(MAKE) -C $(dir $(subst $(obj),,$@))
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$(MAKE) -C $(dir $(subst $(obj),,$@))
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$(SUBDIRS):
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$(SUBDIRS): $(obj)include/autoconf.mk
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$(MAKE) -C $@ all
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$(MAKE) -C $@ all
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$(NAND_SPL): $(VERSION_FILE)
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$(NAND_SPL): $(VERSION_FILE) $(obj)include/autoconf.mk
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$(MAKE) -C nand_spl/board/$(BOARDDIR) all
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$(MAKE) -C nand_spl/board/$(BOARDDIR) all
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$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin
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$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
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cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
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cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
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$(VERSION_FILE):
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$(VERSION_FILE):
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@ -33,7 +33,8 @@
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN)
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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@ -139,7 +140,7 @@ long int fixed_sdram (void)
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im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
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im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
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im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
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im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
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im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
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im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
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im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU;
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im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
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im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
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im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
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im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
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im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
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im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
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im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
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@ -180,9 +181,17 @@ int checkboard (void)
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{
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{
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ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
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ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
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uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
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uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile unsigned long *reg;
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int i;
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printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
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printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
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brd_rev, cpld_rev);
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brd_rev, cpld_rev);
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/* change the slew rate on all pata pins to max */
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reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]);
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for (i = 0; i < 9; i++)
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reg[i] |= 0x00000003;
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return 0;
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return 0;
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}
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}
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@ -192,13 +192,6 @@ int board_early_init_f (void)
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*/
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*/
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mtsdr(SDR0_SRST, 0);
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mtsdr(SDR0_SRST, 0);
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/*
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* Configure FPGA register with PCIe reset
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*/
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out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */
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mdelay(50);
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out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */
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/* Configure 405EX for NAND usage */
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/* Configure 405EX for NAND usage */
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val = SDR0_CUST0_MUX_NDFC_SEL |
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val = SDR0_CUST0_MUX_NDFC_SEL |
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SDR0_CUST0_NDFC_ENABLE |
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SDR0_CUST0_NDFC_ENABLE |
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@ -214,6 +207,13 @@ int board_early_init_f (void)
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val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
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val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
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mtsdr(SDR0_PFC1, val);
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mtsdr(SDR0_PFC1, val);
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/*
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* Configure FPGA register with PCIe reset
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*/
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out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
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mdelay(50);
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out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
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return 0;
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return 0;
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}
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}
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@ -35,7 +35,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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clean:
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rm -f $(OBJS) $(SOBJS)
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rm -f $(OBJS) $(SOBJS)
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File diff suppressed because it is too large
Load Diff
@ -354,9 +354,9 @@
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_HOSTNAME ads5121
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#define CONFIG_HOSTNAME ads5121
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#define CONFIG_BOOTFILE uImage
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#define CONFIG_BOOTFILE ads5121/uImage
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#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
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#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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@ -368,43 +368,47 @@
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"echo"
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"echo"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"u-boot_addr_r=200000\0" \
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"kernel_addr_r=200000\0" \
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"fdt_addr_r=400000\0" \
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"ramdisk_addr_r=500000\0" \
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"u-boot_addr=FFF00000\0" \
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"kernel_addr=FC000000\0" \
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"fdt_addr=FC2C0000\0" \
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"ramdisk_addr=FC300000\0" \
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"ramdiskfile=ads5121/uRamdisk\0" \
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"fdtfile=ads5121/ads5121.dtb\0" \
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"u-boot=ads5121/u-boot.bin\0" \
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"netdev=eth0\0" \
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"netdev=eth0\0" \
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"consdev=ttyPSC0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"addtty=setenv bootargs ${bootargs} " \
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"console=${consdev},${baudrate}\0" \
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"flash_nfs=run nfsargs addip addtty;" \
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"bootm ${kernel_addr_r} - ${fdt_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
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"bootm\0" \
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"tftp ${fdt_addr_r} ${fdtfile};" \
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"load=tftp 200000 /tftpboot/ads5121/u-boot.bin\0" \
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"run nfsargs addip addtty;" \
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"update=protect off FFF00000 +${filesize};" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"era FFF00000 +${filesize};cp.b 200000 FFF00000 ${filesize}\0" \
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"net_self=tftp ${kernel_addr_r} ${bootfile};" \
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"upd=run load;run update\0" \
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"tftp ${ramdisk_addr_r} ${ramdiskfile};" \
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"tftp ${fdt_addr} ${fdtfile};" \
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"run ramargs addip addtty;" \
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"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr}\0"\
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"load=tftp ${u-boot_addr} ${u-boot}\0" \
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"update=protect off ${u-boot_addr} +${filesize};" \
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"era ${u-boot_addr} +${filesize};" \
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"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
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"upd=run load update\0" \
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""
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""
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_LIBFDT 1
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@ -345,6 +345,15 @@
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/* Indexes in regs array */
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/* Indexes in regs array */
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#define MEM_IDX 0x00
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#define MEM_IDX 0x00
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#define PATA_CE1_IDX 0x2e
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#define PATA_CE2_IDX 0x2f
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#define PATA_ISOLATE_IDX 0x30
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#define PATA_IOR_IDX 0x31
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#define PATA_IOW_IDX 0x32
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#define PATA_IOCHRDY_IDX 0x33
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#define PATA_INTRQ_IDX 0x34
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#define PATA_DRQ_IDX 0x35
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#define PATA_DACK_IDX 0x36
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#define SPDIF_TXCLOCK_IDX 0x73
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#define SPDIF_TXCLOCK_IDX 0x73
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#define SPDIF_TX_IDX 0x74
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#define SPDIF_TX_IDX 0x74
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#define SPDIF_RX_IDX 0x75
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#define SPDIF_RX_IDX 0x75
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