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boards: ls1088a: Add support of I2C driver model

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DM_I2C_COMPAT is a compatibility layer that allows using the non-DM
I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch
solves the problem that the i2c-related api of the ls1088a platform
does not support dm.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Chuanhua Han 2019-07-23 18:43:11 +08:00 committed by Prabhakar Kushwaha
parent 292370df1c
commit 5dd043a082
3 changed files with 151 additions and 2 deletions
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148
board/freescale/ls1088a/ls1088a.c
View File

@ -374,7 +374,15 @@ int select_i2c_ch_pca9547(u8 ch)
{ {
int ret; int ret;
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, 0, &ch, 1);
#endif
if (ret) { if (ret) {
puts("PCA: failed to select proper channel\n"); puts("PCA: failed to select proper channel\n");
return ret; return ret;
@ -393,38 +401,89 @@ void board_retimer_init(void)
/* Access to Control/Shared register */ /* Access to Control/Shared register */
reg = 0x0; reg = 0x0;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
#else
struct udevice *dev;
i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
dm_i2c_write(dev, 0xff, &reg, 1);
#endif
/* Read device revision and ID */ /* Read device revision and ID */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1); i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
#else
dm_i2c_read(dev, 1, &reg, 1);
#endif
debug("Retimer version id = 0x%x\n", reg); debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */ /* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c; reg = 0x0c;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
#else
dm_i2c_write(dev, 0xff, &reg, 1);
#endif
/* Reset Channel Registers */ /* Reset Channel Registers */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1); i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
#else
dm_i2c_read(dev, 0, &reg, 1);
#endif
reg |= 0x4; reg |= 0x4;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
#else
dm_i2c_write(dev, 0, &reg, 1);
#endif
/* Set data rate as 10.3125 Gbps */ /* Set data rate as 10.3125 Gbps */
reg = 0x90; reg = 0x90;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x60, &reg, 1);
#endif
reg = 0xb3; reg = 0xb3;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x61, &reg, 1);
#endif
reg = 0x90; reg = 0x90;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x62, &reg, 1);
#endif
reg = 0xb3; reg = 0xb3;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x63, &reg, 1);
#endif
reg = 0xcd; reg = 0xcd;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x64, &reg, 1);
#endif
/* Select VCO Divider to full rate (000) */ /* Select VCO Divider to full rate (000) */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1); i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
#else
dm_i2c_read(dev, 0x2F, &reg, 1);
#endif
reg &= 0x0f; reg &= 0x0f;
reg |= 0x70; reg |= 0x70;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x2F, &reg, 1);
#endif
#ifdef CONFIG_TARGET_LS1088AQDS #ifdef CONFIG_TARGET_LS1088AQDS
/* Retimer is connected to I2C1_CH5 */ /* Retimer is connected to I2C1_CH5 */
@ -432,38 +491,88 @@ void board_retimer_init(void)
/* Access to Control/Shared register */ /* Access to Control/Shared register */
reg = 0x0; reg = 0x0;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
#else
i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
dm_i2c_write(dev, 0xff, &reg, 1);
#endif
/* Read device revision and ID */ /* Read device revision and ID */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1); i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
#else
dm_i2c_read(dev, 1, &reg, 1);
#endif
debug("Retimer version id = 0x%x\n", reg); debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */ /* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c; reg = 0x0c;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
#else
dm_i2c_write(dev, 0xff, &reg, 1);
#endif
/* Reset Channel Registers */ /* Reset Channel Registers */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1); i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
#else
dm_i2c_read(dev, 0, &reg, 1);
#endif
reg |= 0x4; reg |= 0x4;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
#else
dm_i2c_write(dev, 0, &reg, 1);
#endif
/* Set data rate as 10.3125 Gbps */ /* Set data rate as 10.3125 Gbps */
reg = 0x90; reg = 0x90;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x60, &reg, 1);
#endif
reg = 0xb3; reg = 0xb3;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x61, &reg, 1);
#endif
reg = 0x90; reg = 0x90;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x62, &reg, 1);
#endif
reg = 0xb3; reg = 0xb3;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x63, &reg, 1);
#endif
reg = 0xcd; reg = 0xcd;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x64, &reg, 1);
#endif
/* Select VCO Divider to full rate (000) */ /* Select VCO Divider to full rate (000) */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1); i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
#else
dm_i2c_read(dev, 0x2F, &reg, 1);
#endif
reg &= 0x0f; reg &= 0x0f;
reg |= 0x70; reg |= 0x70;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x2F, &reg, 1);
#endif
#endif #endif
/*return the default channel*/ /*return the default channel*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@ -500,16 +609,30 @@ int get_serdes_volt(void)
u8 chan = PWM_CHANNEL0; u8 chan = PWM_CHANNEL0;
/* Select the PAGE 0 using PMBus commands PAGE for VDD */ /* Select the PAGE 0 using PMBus commands PAGE for VDD */
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_SVDD_MONITOR_ADDR, ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1); PMBUS_CMD_PAGE, 1, &chan, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
&chan, 1);
#endif
if (ret) { if (ret) {
printf("VID: failed to select VDD Page 0\n"); printf("VID: failed to select VDD Page 0\n");
return ret; return ret;
} }
/* Read the output voltage using PMBus command READ_VOUT */ /* Read the output voltage using PMBus command READ_VOUT */
#ifndef CONFIG_DM_I2C
ret = i2c_read(I2C_SVDD_MONITOR_ADDR, ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
#else
dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
#endif
if (ret) { if (ret) {
printf("VID: failed to read the volatge\n"); printf("VID: failed to read the volatge\n");
return ret; return ret;
@ -525,8 +648,17 @@ int set_serdes_volt(int svdd)
svdd & 0xFF, (svdd & 0xFF00) >> 8}; svdd & 0xFF, (svdd & 0xFF00) >> 8};
/* Write the desired voltage code to the SVDD regulator */ /* Write the desired voltage code to the SVDD regulator */
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_SVDD_MONITOR_ADDR, ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
(void *)&buff, 5);
#endif
if (ret) { if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n"); printf("VID: I2C failed to write to the volatge regulator\n");
return -1; return -1;
@ -557,8 +689,18 @@ int set_serdes_volt(int svdd)
printf("SVDD changing of RDB\n"); printf("SVDD changing of RDB\n");
/* Read the BRDCFG54 via CLPD */ /* Read the BRDCFG54 via CLPD */
#ifndef CONFIG_DM_I2C
ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
(void *)&brdcfg4, 1);
#endif
if (ret) { if (ret) {
printf("VID: I2C failed to read the CPLD BRDCFG4\n"); printf("VID: I2C failed to read the CPLD BRDCFG4\n");
return -1; return -1;
@ -567,8 +709,14 @@ int set_serdes_volt(int svdd)
brdcfg4 = brdcfg4 | 0x08; brdcfg4 = brdcfg4 | 0x08;
/* Write to the BRDCFG4 */ /* Write to the BRDCFG4 */
#ifndef CONFIG_DM_I2C
ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
(void *)&brdcfg4, 1);
#endif
if (ret) { if (ret) {
debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
return -1; return -1;

3
include/configs/ls1088a_common.h
View File

@ -67,7 +67,10 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
/* I2C */ /* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C
#endif
/* Serial Port */ /* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_SERIAL

2
include/configs/ls1088ardb.h
View File

@ -269,9 +269,7 @@
* RTC configuration * RTC configuration
*/ */
#define RTC #define RTC
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#define CONFIG_CMD_DATE
#endif #endif
/* EEPROM */ /* EEPROM */