add c structures for SoC access

* add's c structures for SoC access to pheriperials head files

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>

include/asm-arm/arch-at91/at91_matrix.h

@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_MATRIX_H
+#define AT91_MATRIX_H
+
+#ifdef __ASSEMBLY__
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x11C)
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x30)
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x120)
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x128)
+#else
+#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
+#endif
+
+#define AT91_ASM_MATRIX_MCFG	AT91_MATRIX_BASE
+
+#else
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_MATRIX_MASTERS	6
+#define AT91_MATRIX_SLAVES	5
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_MATRIX_MASTERS	1
+#define AT91_MATRIX_SLAVES	5
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_MATRIX_MASTERS	9
+#define AT91_MATRIX_SLAVES	7
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MASTERS	11
+#define AT91_MATRIX_SLAVES	8
+#else
+#error CPU not supported. Please update at91_matrix.h
+#endif
+
+typedef struct at91_priority {
+	u32	a;
+	u32	b;
+} at91_priority_t;
+
+typedef struct at91_matrix {
+	u32		mcfg[AT91_MATRIX_MASTERS];
+#if defined(CONFIG_AT91SAM9261)
+	u32		scfg[AT91_MATRIX_SLAVES];
+	u32		res61_1[3];
+	u32		tcr;
+	u32		res61_2[2];
+	u32		csa;
+	u32		pucr;
+	u32		res61_3[114];
+#else
+	u32		reserve1[16 - AT91_MATRIX_MASTERS];
+	u32		scfg[AT91_MATRIX_SLAVES];
+	u32		reserve2[16 - AT91_MATRIX_SLAVES];
+	at91_priority_t	pr[AT91_MATRIX_SLAVES];
+	u32		reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
+	u32		mrcr;		/* 0x100 Master Remap Control */
+	u32		reserve4[3];
+#if	defined(CONFIG_AT91SAM9G45)
+	u32		ccr[52]		/* 0x110 - 0x1E0 Chip Configuration */
+	u32		womr;		/* 0x1E4 Write Protect Mode  */
+	u32		wpsr;		/* 0x1E8 Write Protect Status */
+	u32		resg45_1[10];
+#elif defined(CONFIG_AT91SAM9260)  || defined(CONFIG_AT91SAM9G20)
+	u32		res60_1[3];
+	u32		csa;
+	u32		res60_2[56];
+#elif defined(CONFIG_AT91SAM9263)
+	u32		res63_1;
+	u32		tcmr;
+	u32		res63_2[2];
+	u32		csa[2];
+	u32		res63_3[54];
+#else
+	u32		reserve5[60];
+#endif
+#endif
+} at91_matrix_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_CSA_DBPUC		0x00000100
+#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V	0x00000000
+#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V	0x00010000
+
+#define AT91_MATRIX_CSA_EBI_CS1A	0x00000002
+#define AT91_MATRIX_CSA_EBI_CS3A	0x00000008
+#define AT91_MATRIX_CSA_EBI_CS4A	0x00000010
+#define AT91_MATRIX_CSA_EBI_CS5A	0x00000020
+
+#define AT91_MATRIX_CSA_EBI1_CS2A	0x00000008
+
+#endif

include/asm-arm/arch-at91/at91_pdc.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
+
+typedef struct at91_pdc {
+	u32	rpr;		/* 0x100 Receive Pointer Register */
+	u32	rcr;		/* 0x104 Receive Counter Register */
+	u32	tpr;		/* 0x108 Transmit Pointer Register */
+	u32	tcr;		/* 0x10C Transmit Counter Register */
+	u32	pnpr;		/* 0x110 Receive Next Pointer Register */
+	u32	pncr;		/* 0x114 Receive Next Counter Register */
+	u32	tnpr;		/* 0x118 Transmit Next Pointer Register */
+	u32	tncr;		/* 0x11C Transmit Next Counter Register */
+	u32	ptcr;		/* 0x120 Transfer Control Register */
+	u32	ptsr;		/* 0x124 Transfer Status Register */
+} at91_pdc_t;
+
+#endif

include/asm-arm/arch-at91/at91_pio.h

@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  *
  * Parallel I/O Controller (PIO) - System peripherals registers.
  * Based on AT91RM9200 datasheet revision E.
@@ -16,6 +17,101 @@
 #ifndef AT91_PIO_H
 #define AT91_PIO_H
 
+
+#define AT91_ASM_PIO_RANGE	0x200
+#define AT91_ASM_PIOC_PDR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x04)
+#define AT91_ASM_PIOC_PUDR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x60)
+
+#define AT91_ASM_PIOD_PDR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x04)
+#define AT91_ASM_PIOD_PUDR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x60)
+#define AT91_ASM_PIOD_ASR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x70)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_port {
+	u32	per;		/* 0x00 PIO Enable Register */
+	u32	pdr;		/* 0x04 PIO Disable Register */
+	u32	psr;		/* 0x08 PIO Status Register */
+	u32	reserved0;
+	u32	oer;		/* 0x10 Output Enable Register */
+	u32	odr;		/* 0x14 Output Disable Registerr */
+	u32	osr;		/* 0x18 Output Status Register */
+	u32	reserved1;
+	u32	ifer;		/* 0x20 Input Filter Enable Register */
+	u32	ifdr;		/* 0x24 Input Filter Disable Register */
+	u32	ifsr;		/* 0x28 Input Filter Status Register */
+	u32	reserved2;
+	u32	sodr;		/* 0x30 Set Output Data Register */
+	u32	codr;		/* 0x34 Clear Output Data Register */
+	u32	odsr;		/* 0x38 Output Data Status Register */
+	u32	pdsr;		/* 0x3C Pin Data Status Register */
+	u32	ier;		/* 0x40 Interrupt Enable Register */
+	u32	idr;		/* 0x44 Interrupt Disable Register */
+	u32	imr;		/* 0x48 Interrupt Mask Register */
+	u32	isr;		/* 0x4C Interrupt Status Register */
+	u32	mder;		/* 0x50 Multi-driver Enable Register */
+	u32	mddr;		/* 0x54 Multi-driver Disable Register */
+	u32	mdsr;		/* 0x58 Multi-driver Status Register */
+	u32	reserved3;
+	u32	pudr;		/* 0x60 Pull-up Disable Register */
+	u32	puer;		/* 0x64 Pull-up Enable Register */
+	u32	pusr;		/* 0x68 Pad Pull-up Status Register */
+	u32	reserved4;
+	u32	asr;		/* 0x70 Select A Register */
+	u32	bsr;		/* 0x74 Select B Register */
+	u32	absr;		/* 0x78 AB Select Status Register */
+	u32	reserved5[9];	/*  */
+	u32	ower;		/* 0xA0 Output Write Enable Register */
+	u32	owdr;		/* 0xA4 Output Write Disable Register */
+	u32	owsr;		/* OxA8 utput Write Status Register */
+	u32	reserved6[85];
+} at91_port_t;
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
+	defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20)
+#define AT91_PIO_PORTS	3
+#elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \
+	defined(CONFIG_AT91SAM9M10G45)
+#define AT91_PIO_PORTS	5
+#elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \
+	defined(CONFIG_AT91SAM9RL)
+#define AT91_PIO_PORTS	4
+#else
+#error "Unsupported cpu. Please update at91_pio.h"
+#endif
+
+typedef union at91_pio {
+	struct {
+		at91_port_t	pioa;
+		at91_port_t	piob;
+		at91_port_t	pioc;
+	#if (AT91_PIO_PORTS > 3)
+		at91_port_t	piod;
+	#endif
+	#if (AT91_PIO_PORTS > 4)
+		at91_port_t	pioe;
+	#endif
+	} ;
+	at91_port_t port[AT91_PIO_PORTS];
+} at91_pio_t;
+
+#endif
+
+#define AT91_PIN_TO_MASK(x)	(1<<x)
+#define AT91_PORTPIN(PORT, PIN)	((0x0##PORT - 9) * 32 + ((PIN) & 0x1F))
+#define	AT91_PIO_PORTA		0x0
+#define	AT91_PIO_PORTB		0x1
+#define	AT91_PIO_PORTC		0x2
+#define	AT91_PIO_PORTD		0x3
+#define	AT91_PIO_PORTE		0x4
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define PIO_PER		0x00	/* Enable Register */
 #define PIO_PDR		0x04	/* Disable Register */
 #define PIO_PSR		0x08	/* Status Register */
@@ -45,5 +141,6 @@
 #define PIO_OWER	0xa0	/* Output Write Enable Register */
 #define PIO_OWDR	0xa4	/* Output Write Disable Register */
 #define PIO_OWSR	0xa8	/* Output Write Status Register */
+#endif
 
 #endif

include/asm-arm/arch-at91/at91_pit.h

@@ -16,6 +16,20 @@
 #ifndef AT91_PIT_H
 #define AT91_PIT_H
 
+typedef struct at91_pit {
+	u32	mr;	/* 0x00 Mode Register */
+	u32	sr;	/* 0x04 Status Register */
+	u32	pivr;	/* 0x08 Periodic Interval Value Register */
+	u32	piir;	/* 0x0C Periodic Interval Image Register */
+} at91_pit_t;
+
+#define		AT91_PIT_MR_IEN		0x02000000
+#define		AT91_PIT_MR_EN		0x01000000
+#define		AT91_PIT_MR_PIV_MASK	(x & 0x000fffff)
+#define		AT91_PIT_MR_PIV(x)	(x & AT91_PIT_MR_PIV_MASK)
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
 #define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
 #define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
@@ -29,4 +43,5 @@
 #define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
 #define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
 
+#endif /* CONFIG_AT91_LEGACY */
 #endif

include/asm-arm/arch-at91/at91_pmc.h

@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  *
  * Power Management Controller (PMC) - System peripherals registers.
  * Based on AT91RM9200 datasheet revision E.
@@ -16,6 +17,95 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
+#define	AT91_ASM_PMC_MOR	(AT91_PMC_BASE + 0x20)
+#define	AT91_ASM_PMC_PLLAR	(AT91_PMC_BASE + 0x28)
+#define	AT91_ASM_PMC_PLLBR	(AT91_PMC_BASE + 0x2c)
+#define AT91_ASM_PMC_MCKR	(AT91_PMC_BASE + 0x30)
+#define AT91_ASM_PMC_SR		(AT91_PMC_BASE + 0x68)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+typedef struct at91_pmc {
+	u32	scer;		/* 0x00 System Clock Enable Register */
+	u32	scdr;		/* 0x04 System Clock Disable Register */
+	u32	scsr;		/* 0x08 System Clock Status Register */
+	u32	reserved0;
+	u32	pcer;		/* 0x10 Peripheral Clock Enable Register */
+	u32	pcdr;		/* 0x14 Peripheral Clock Disable Register */
+	u32	pcsr;		/* 0x18 Peripheral Clock Status Register */
+	u32	reserved1;
+	u32	mor;		/* 0x20 Main Oscilator Register */
+	u32	mcfr;		/* 0x24 Main Clock Frequency Register */
+	u32	pllar;		/* 0x28 PLL A Register */
+	u32	pllbr;		/* 0x2C PLL B Register */
+	u32	mckr;		/* 0x30 Master Clock Register */
+	u32	reserved2[3];
+	u32	pck[4];		/* 0x40 Programmable Clock Register 0 - 3 */
+	u32	reserved3[4];
+	u32	ier;		/* 0x60 Interrupt Enable Register */
+	u32	idr;		/* 0x64 Interrupt Disable Register */
+	u32	sr;		/* 0x68 Status Register */
+	u32	imr;		/* 0x6C Interrupt Mask Register */
+	u32	reserved4[4];
+	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
+	u32	reserved5[21];
+	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
+	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
+	u32	reserved8[5];
+} at91_pmc_t;
+
+#endif	/* end not assembly */
+
+#define AT91_PMC_MOR_MOSCEN		0x01
+#define AT91_PMC_MOR_OSCBYPASS		0x02
+#define AT91_PMC_MOR_OSCOUNT(x)		((x & 0xff) << 8)
+
+#define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
+#define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
+#define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
+#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
+#define AT91_PMC_PLLAR_29		0x20000000
+#define AT91_PMC_PLLBR_USBDIV_1		0x00000000
+#define AT91_PMC_PLLBR_USBDIV_2		0x10000000
+#define AT91_PMC_PLLBR_USBDIV_4		0x20000000
+
+#define AT91_PMC_MCKR_CSS_SLOW		0x00000000
+#define AT91_PMC_MCKR_CSS_MAIN		0x00000001
+#define AT91_PMC_MCKR_CSS_PLLA		0x00000002
+#define AT91_PMC_MCKR_CSS_PLLB		0x00000003
+#define AT91_PMC_MCKR_CSS_MASK		0x00000003
+
+#define AT91_PMC_MCKR_PRES_1		0x00000000
+#define AT91_PMC_MCKR_PRES_2		0x00000004
+#define AT91_PMC_MCKR_PRES_4		0x00000008
+#define AT91_PMC_MCKR_PRES_8		0x0000000C
+#define AT91_PMC_MCKR_PRES_16		0x00000010
+#define AT91_PMC_MCKR_PRES_32		0x00000014
+#define AT91_PMC_MCKR_PRES_64		0x00000018
+#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
+
+#define AT91_PMC_MCKR_MDIV_1		0x00000000
+#define AT91_PMC_MCKR_MDIV_2		0x00000100
+#define AT91_PMC_MCKR_MDIV_4		0x00000200
+#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
+
+#define AT91_PMC_MCKR_PLLADIV_1		0x00001000
+#define AT91_PMC_MCKR_PLLADIV_2		0x00002000
+
+#define AT91_PMC_IXR_MOSCS		0x00000001
+#define AT91_PMC_IXR_LOCKA		0x00000002
+#define AT91_PMC_IXR_LOCKB		0x00000004
+#define AT91_PMC_IXR_MCKRDY		0x00000008
+#define AT91_PMC_IXR_LOCKU		0x00000040
+#define AT91_PMC_IXR_PCKRDY0		0x00000100
+#define AT91_PMC_IXR_PCKRDY1		0x00000200
+#define AT91_PMC_IXR_PCKRDY2		0x00000400
+#define AT91_PMC_IXR_PCKRDY3		0x00000800
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
 #define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
 
@@ -117,4 +207,5 @@
 
 #define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
 
+#endif /* CONFIG_AT91_LEGACY */
 #endif

include/asm-arm/arch-at91/at91_rstc.h

@@ -16,11 +16,37 @@
 #ifndef AT91_RSTC_H
 #define AT91_RSTC_H
 
+#define AT91_ASM_RSTC_MR	(AT91_RSTC_BASE + 0x08)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_rstc {
+	u32	cr;	/* Reset Controller Control Register */
+	u32	sr;	/* Reset Controller Status Register */
+	u32	mr;	/* Reset Controller Mode Register */
+} at91_rstc_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_RSTC_KEY		0xA5000000
+
+#define AT91_RSTC_CR_PROCRST	0x00000001
+#define AT91_RSTC_CR_PERRST	0x00000004
+#define AT91_RSTC_CR_EXTRST	0x00000008
+
+#define AT91_RSTC_MR_URSTEN	0x00000001
+#define AT91_RSTC_MR_URSTIEN	0x00000010
+#define AT91_RSTC_MR_ERSTL(x)	((x & 0xf) << 8)
+#define AT91_RSTC_MR_ERSTL_MASK	0x0000FF00
+
+#define AT91_RSTC_SR_NRSTL	0x00010000
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_RSTC_CR		(AT91_RSTC + 0x00)	/* Reset Controller Control Register */
 #define		AT91_RSTC_PROCRST	(1 << 0)		/* Processor Reset */
 #define		AT91_RSTC_PERRST	(1 << 2)		/* Peripheral Reset */
 #define		AT91_RSTC_EXTRST	(1 << 3)		/* External Reset */
-#define		AT91_RSTC_KEY		(0xa5 << 24)		/* KEY Password */
 
 #define AT91_RSTC_SR		(AT91_RSTC + 0x04)	/* Reset Controller Status Register */
 #define		AT91_RSTC_URSTS		(1 << 0)		/* User Reset Status */
@@ -38,4 +64,6 @@
 #define		AT91_RSTC_URSTIEN	(1 << 4)		/* User Reset Interrupt Enable */
 #define		AT91_RSTC_ERSTL		(0xf << 8)		/* External Reset Length */
 
+#endif /* CONFIG_AT91_LEGACY */
+
 #endif

include/asm-arm/arch-at91/at91_spi.h

@@ -16,6 +16,25 @@
 #ifndef AT91_SPI_H
 #define AT91_SPI_H
 
+#include <asm/arch/at91_pdc.h>
+
+typedef struct at91_spi {
+	u32		cr;		/* 0x00 Control Register */
+	u32		mr;		/* 0x04 Mode Register */
+	u32		rdr;		/* 0x08 Receive Data Register */
+	u32		tdr;		/* 0x0C Transmit Data Register */
+	u32		sr;		/* 0x10 Status Register */
+	u32		ier;		/* 0x14 Interrupt Enable Register */
+	u32		idr;		/* 0x18 Interrupt Disable Register */
+	u32		imr;		/* 0x1C Interrupt Mask Register */
+	u32		reserve1[4];
+	u32		csr[4];		/* 0x30 Chip Select Register 0-3 */
+	u32		reserve2[48];
+	at91_pdc_t	pdc;
+} at91_spi_t;
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_SPI_CR			0x00		/* Control Register */
 #define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
 #define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */
@@ -102,4 +121,6 @@
 
 #define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
 
+#endif /* CONFIG_AT91_LEGACY */
+
 #endif

include/asm-arm/arch-at91/at91_wdt.h

@@ -17,6 +17,34 @@
 #ifndef AT91_WDT_H
 #define AT91_WDT_H
 
+#ifdef __ASSEMBLY__
+
+#define AT91_ASM_WDT_MR	(AT91_WDT_BASE +  0x04)
+
+#else
+
+typedef struct at91_wdt {
+	u32	cr;
+	u32	mr;
+	u32	sr;
+} at91_wdt_t;
+
+#endif
+
+#define AT91_WDT_CR_WDRSTT		1
+#define AT91_WDT_CR_KEY			0xa5000000	/* KEY Password */
+
+#define AT91_WDT_MR_WDV(x)		(x & 0xfff)
+#define AT91_WDT_MR_WDFIEN		0x00001000
+#define AT91_WDT_MR_WDRSTEN		0x00002000
+#define AT91_WDT_MR_WDRPROC		0x00004000
+#define AT91_WDT_MR_WDDIS		0x00008000
+#define AT91_WDT_MR_WDD(x)		((x & 0xfff) << 16)
+#define AT91_WDT_MR_WDDBGHLT		0x10000000
+#define AT91_WDT_MR_WDIDLEHLT		0x20000000
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_WDT_CR		(AT91_WDT + 0x00)	/* Watchdog Control Register */
 #define		AT91_WDT_WDRSTT		(1    << 0)		/* Restart */
 #define		AT91_WDT_KEY		(0xa5 << 24)		/* KEY Password */
@@ -35,4 +63,5 @@
 #define		AT91_WDT_WDUNF		(1 << 0)		/* Watchdog Underflow */
 #define		AT91_WDT_WDERR		(1 << 1)		/* Watchdog Error */
 
+#endif /* CONFIG_AT91_LEGACY */
 #endif

include/asm-arm/arch-at91/at91cap9.h

@@ -53,6 +53,13 @@
 #define AT91CAP9_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
 #define AT91CAP9_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
 
+#define AT91_PIO_BASE	0xfffff200
+#define AT91_PMC_BASE	0xfffffc00
+#define AT91_RSTC_BASE	0xfffffd00
+#define AT91_PIT_BASE	0xfffffd30
+
+#ifdef CONFIG_AT91_LEGACY
+
 /*
  * User Peripheral physical base addresses.
  */
@@ -119,6 +126,7 @@
 #define		AT91CAP9_SCKCR_OSCSEL_RC	(0 << 3)
 #define		AT91CAP9_SCKCR_OSCSEL_32	(1 << 3)
 
+#endif /* CONFIG_AT91_LEGACY */
 /*
  * Internal Memory.
  */

include/asm-arm/arch-at91/at91sam9260.h

@@ -49,6 +49,18 @@
 #define AT91SAM9260_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
 #define AT91SAM9260_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
 
+#define AT91_EMAC_BASE		0xfffc4000
+#define AT91_SDRAMC_BASE	0xffffea00
+#define AT91_SMC_BASE		0xffffec00
+#define AT91_MATRIX_BASE	0xffffee00
+#define AT91_PIO_BASE		0xfffff400
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
+
 /*
  * User Peripheral physical base addresses.
  */
@@ -105,6 +117,8 @@
 #define AT91_USART4	AT91SAM9260_BASE_US4
 #define AT91_USART5	AT91SAM9260_BASE_US5
 
+#endif /* CONFIG_AT91_LEGACY */
+
 /*
  * Internal Memory.
  */

include/asm-arm/arch-at91/at91sam9261.h

@@ -43,6 +43,16 @@
 #define AT91SAM9261_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
 #define AT91SAM9261_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
 
+#define AT91_SDRAMC_BASE	0xffffea00
+#define AT91_SMC_BASE		0xffffec00
+#define AT91_MATRIX_BASE	0xffffee00
+#define AT91_PIO_BASE		0xfffff400
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
 
 /*
  * User Peripheral physical base addresses.
@@ -64,7 +74,6 @@
 #define AT91SAM9261_BASE_SPI1		0xfffcc000
 #define AT91_BASE_SYS			0xffffea00
 
-
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
@@ -88,6 +97,7 @@
 #define AT91_USART1	AT91SAM9261_BASE_US1
 #define AT91_USART2	AT91SAM9261_BASE_US2
 
+#endif /* CONFIG_AT91_LEGACY */
 
 /*
  * Internal Memory.

include/asm-arm/arch-at91/at91sam9263.h

@@ -47,6 +47,24 @@
 #define AT91SAM9263_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
 #define AT91SAM9263_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
 
+#define AT91_EMAC_BASE		0xfffbc000
+#define AT91_ECC0_BASE		0xffffe000
+#define AT91_SDRAMC0_BASE	0xffffe200
+#define AT91_SMC0_BASE		0xffffe400
+#define AT91_ECC1_BASE		0xffffe600
+#define AT91_SDRAMC1_BASE	0xffffe800
+#define AT91_SMC1_BASE		0xffffea00
+#define AT91_MATRIX_BASE	0xffffec00
+#define AT91_CCFG_BASE		0xffffed10
+#define AT91_DBGU_BASE		0xffffee00
+#define AT91_AIC_BASE		0xfffff000
+#define AT91_PIO_BASE		0xfffff200
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
 
 /*
  * User Peripheral physical base addresses.
@@ -108,6 +126,8 @@
 #define AT91_SMC	AT91_SMC0
 #define AT91_SDRAMC	AT91_SDRAMC0
 
+#endif /* CONFIG_AT91_LEGACY */
+
 /*
  * Internal Memory.
  */

include/asm-arm/arch-at91/at91sam9_sdramc.h

@@ -17,6 +17,19 @@
 #ifndef AT91SAM9_SDRAMC_H
 #define AT91SAM9_SDRAMC_H
 
+#ifdef __ASSEMBLY__
+
+#ifndef AT91_SDRAMC_BASE
+#define AT91_SDRAMC_BASE	AT91_SDRAMC0_BASE
+#endif
+
+#define AT91_ASM_SDRAMC_MR	AT91_SDRAMC_BASE
+#define AT91_ASM_SDRAMC_TR	(AT91_SDRAMC_BASE + 0x04)
+#define AT91_ASM_SDRAMC_CR	(AT91_SDRAMC_BASE + 0x08)
+#define AT91_ASM_SDRAMC_MDR	(AT91_SDRAMC_BASE + 0x24)
+
+#endif
+
 /* SDRAM Controller (SDRAMC) registers */
 #define AT91_SDRAMC_MR		(AT91_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
 #define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */

include/asm-arm/arch-at91/at91sam9_smc.h

@@ -16,6 +16,68 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
 
+#ifdef __ASSEMBLY__
+
+#ifndef AT91_SMC_BASE
+#define AT91_SMC_BASE	AT91_SMC0_BASE
+#endif
+
+#define AT91_ASM_SMC_SETUP0	AT91_SMC_BASE
+#define AT91_ASM_SMC_PULSE0	(AT91_SMC_BASE + 0x04)
+#define AT91_ASM_SMC_CYCLE0	(AT91_SMC_BASE + 0x08)
+#define AT91_ASM_SMC_MODE0	(AT91_SMC_BASE + 0x0C)
+
+#else
+
+typedef struct	at91_cs {
+	u32	setup;		/* 0x00 SMC Setup Register */
+	u32	pulse;		/* 0x04 SMC Pulse Register */
+	u32	cycle;		/* 0x08 SMC Cycle Register */
+	u32	mode;		/* 0x0C SMC Mode Register */
+} at91_cs_t;
+
+typedef struct	at91_smc {
+	at91_cs_t	cs[8];
+} at91_smc_t;
+
+#endif /*  __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x)		(x & 0x7f)
+#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x7f) << 8)
+#define AT91_SMC_PULSE_NRD(x)		((x & 0x7f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x7f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
+
+#define AT91_SMC_MODE_RM_NCS		0x00000000
+#define AT91_SMC_MODE_RM_NRD		0x00000001
+#define AT91_SMC_MODE_WM_NCS		0x00000000
+#define AT91_SMC_MODE_WM_NWE		0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
+#define AT91_SMC_MODE_EXNW_READY	0x00000030
+
+#define AT91_SMC_MODE_BAT		0x00000100
+#define AT91_SMC_MODE_DBW_8		0x00000000
+#define AT91_SMC_MODE_DBW_16		0x00001000
+#define AT91_SMC_MODE_DBW_32		0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF		0x00100000
+#define AT91_SMC_MODE_PMEN		0x01000000
+#define AT91_SMC_MODE_PS_4		0x00000000
+#define AT91_SMC_MODE_PS_8		0x10000000
+#define AT91_SMC_MODE_PS_16		0x20000000
+#define AT91_SMC_MODE_PS_32		0x30000000
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_SMC_SETUP(n)	(AT91_SMC + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
 #define		AT91_SMC_NWESETUP	(0x3f << 0)			/* NWE Setup Length */
 #define			AT91_SMC_NWESETUP_(x)	((x) << 0)
@@ -74,3 +136,4 @@
 #endif
 
 #endif
+#endif

include/asm-arm/arch-at91/at91sam9g45.h

@@ -51,6 +51,17 @@
 #define AT91SAM9G45_ID_VDEC	30	/* Video Decoder */
 #define AT91SAM9G45_ID_IRQ0	31	/* Advanced Interrupt Controller */
 
+#define AT91_EMAC_BASE		0xfffbc000
+#define AT91_SMC_BASE		0xffffe800
+#define AT91_MATRIX_BASE	0xffffea00
+#define AT91_PIO_BASE		0xfffff200
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
+
 /*
  * User Peripheral physical base addresses.
  */
@@ -114,6 +125,8 @@
 #define AT91_USART2	AT91SAM9G45_BASE_US2
 #define AT91_USART3	AT91SAM9G45_BASE_US3
 
+#endif
+
 /*
  * Internal Memory.
  */

include/asm-arm/arch-at91/at91sam9rl.h

@@ -44,6 +44,16 @@
 #define AT91SAM9RL_ID_AC97C	24	/* AC97 Controller */
 #define AT91SAM9RL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
 
+#define AT91_SDRAMC_BASE	0xffffea00
+#define AT91_SMC_BASE		0xffffec00
+#define AT91_MATRIX_BASE	0xffffee00
+#define AT91_PIO_BASE		0xfffff400
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
 
 /*
  * User Peripheral physical base addresses.
@@ -68,7 +78,6 @@
 #define AT91SAM9RL_BASE_AC97C	0xfffd8000
 #define AT91_BASE_SYS		0xffffc000
 
-
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
@@ -99,6 +108,7 @@
 #define AT91_USART2	AT91SAM9RL_BASE_US2
 #define AT91_USART3	AT91SAM9RL_BASE_US3
 
+#endif /* CONFIG_AT91_LEGACY */
 
 /*
  * Internal Memory.

include/asm-arm/arch-at91/gpio.h

@@ -18,6 +18,8 @@
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/hardware.h>
 
+#ifdef CONFIG_AT91_LEGACY
+
 #define PIN_BASE		32
 
 #define MAX_GPIO_BANKS		5
@@ -365,3 +367,4 @@ static inline int at91_get_gpio_value(unsigned pin)
 }
 
 #endif
+#endif

include/asm-arm/arch-at91/io.h

@@ -23,6 +23,8 @@
 
 #include <asm/io.h>
 
+#ifdef CONFIG_AT91_LEGACY
+
 static inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
 	void *addr = (void *)AT91_BASE_SYS;
@@ -36,5 +38,6 @@ static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
 
 	__raw_writel(value, addr + reg_offset);
 }
+#endif
 
 #endif