pci: Add all known capability and extended capability ids
Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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@ -318,7 +318,21 @@
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#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
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#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
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#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
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#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
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#define PCI_CAP_ID_DBG 0x0A /* Debug port */
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#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
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#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
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#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
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#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
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#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
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#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
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#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
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#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
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#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
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#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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@ -434,6 +448,10 @@
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#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
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#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
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#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
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#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
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#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
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#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
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/* Include the ID list */
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